Lines Matching refs:gic
40 #include <linux/irqchip/arm-gic.h>
48 #include "irq-gic-common.h"
339 struct gic_chip_data *gic = &gic_data[0];
340 void __iomem *cpu_base = gic_data_cpu_base(gic);
372 handle_domain_irq(gic->domain, irqnr, regs);
423 static u8 gic_get_cpumask(struct gic_chip_data *gic)
425 void __iomem *base = gic_data_dist_base(gic);
448 static void gic_cpu_if_up(struct gic_chip_data *gic)
450 void __iomem *cpu_base = gic_data_cpu_base(gic);
455 if (gic == &gic_data[0] && static_branch_likely(&supports_deactivate_key))
472 static void gic_dist_init(struct gic_chip_data *gic)
476 unsigned int gic_irqs = gic->gic_irqs;
477 void __iomem *base = gic_data_dist_base(gic);
484 cpumask = gic_get_cpumask(gic);
495 static int gic_cpu_init(struct gic_chip_data *gic)
497 void __iomem *dist_base = gic_data_dist_base(gic);
498 void __iomem *base = gic_data_cpu_base(gic);
507 if (gic == &gic_data[0]) {
515 cpu_mask = gic_get_cpumask(gic);
530 gic_cpu_if_up(gic);
558 void gic_dist_save(struct gic_chip_data *gic)
564 if (WARN_ON(!gic))
567 gic_irqs = gic->gic_irqs;
568 dist_base = gic_data_dist_base(gic);
574 gic->saved_spi_conf[i] =
578 gic->saved_spi_target[i] =
582 gic->saved_spi_enable[i] =
586 gic->saved_spi_active[i] =
597 void gic_dist_restore(struct gic_chip_data *gic)
603 if (WARN_ON(!gic))
606 gic_irqs = gic->gic_irqs;
607 dist_base = gic_data_dist_base(gic);
615 writel_relaxed(gic->saved_spi_conf[i],
623 writel_relaxed(gic->saved_spi_target[i],
629 writel_relaxed(gic->saved_spi_enable[i],
636 writel_relaxed(gic->saved_spi_active[i],
643 void gic_cpu_save(struct gic_chip_data *gic)
650 if (WARN_ON(!gic))
653 dist_base = gic_data_dist_base(gic);
654 cpu_base = gic_data_cpu_base(gic);
659 ptr = raw_cpu_ptr(gic->saved_ppi_enable);
663 ptr = raw_cpu_ptr(gic->saved_ppi_active);
667 ptr = raw_cpu_ptr(gic->saved_ppi_conf);
673 void gic_cpu_restore(struct gic_chip_data *gic)
680 if (WARN_ON(!gic))
683 dist_base = gic_data_dist_base(gic);
684 cpu_base = gic_data_cpu_base(gic);
689 ptr = raw_cpu_ptr(gic->saved_ppi_enable);
696 ptr = raw_cpu_ptr(gic->saved_ppi_active);
703 ptr = raw_cpu_ptr(gic->saved_ppi_conf);
712 gic_cpu_if_up(gic);
745 static int gic_pm_init(struct gic_chip_data *gic)
747 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
749 if (WARN_ON(!gic->saved_ppi_enable))
752 gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
754 if (WARN_ON(!gic->saved_ppi_active))
757 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
759 if (WARN_ON(!gic->saved_ppi_conf))
762 if (gic == &gic_data[0])
768 free_percpu(gic->saved_ppi_active);
770 free_percpu(gic->saved_ppi_enable);
775 static int gic_pm_init(struct gic_chip_data *gic)
869 "irqchip/arm/gic:starting",
1028 struct gic_chip_data *gic = d->host_data;
1034 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
1040 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
1044 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
1145 static void gic_init_chip(struct gic_chip_data *gic, struct device *dev,
1149 gic->chip = gic_chip;
1150 gic->chip.name = name;
1151 gic->chip.parent_device = dev;
1154 gic->chip.irq_mask = gic_eoimode1_mask_irq;
1155 gic->chip.irq_eoi = gic_eoimode1_eoi_irq;
1156 gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity;
1159 if (gic == &gic_data[0]) {
1160 gic->chip.irq_set_affinity = gic_set_affinity;
1161 gic->chip.ipi_send_mask = gic_ipi_send_mask;
1165 static int gic_init_bases(struct gic_chip_data *gic,
1170 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
1174 gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
1175 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
1176 if (WARN_ON(!gic->dist_base.percpu_base ||
1177 !gic->cpu_base.percpu_base)) {
1185 unsigned long offset = gic->percpu_offset * core_id;
1186 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) =
1187 gic->raw_dist_base + offset;
1188 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) =
1189 gic->raw_cpu_base + offset;
1195 WARN(gic->percpu_offset,
1197 gic->percpu_offset);
1198 gic->dist_base.common_base = gic->raw_dist_base;
1199 gic->cpu_base.common_base = gic->raw_cpu_base;
1206 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
1210 gic->gic_irqs = gic_irqs;
1213 gic->domain = irq_domain_create_linear(handle, gic_irqs,
1215 gic);
1232 gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base,
1233 16, &gic_irq_domain_ops, gic);
1236 if (WARN_ON(!gic->domain)) {
1241 gic_dist_init(gic);
1242 ret = gic_cpu_init(gic);
1246 ret = gic_pm_init(gic);
1253 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
1254 free_percpu(gic->dist_base.percpu_base);
1255 free_percpu(gic->cpu_base.percpu_base);
1261 static int __init __gic_init_bases(struct gic_chip_data *gic,
1267 if (WARN_ON(!gic || gic->domain))
1270 if (gic == &gic_data[0]) {
1284 if (static_branch_likely(&supports_deactivate_key) && gic == &gic_data[0]) {
1286 gic_init_chip(gic, NULL, name, true);
1288 name = kasprintf(GFP_KERNEL, "GIC-%d", (int)(gic-&gic_data[0]));
1289 gic_init_chip(gic, NULL, name, false);
1292 ret = gic_init_bases(gic, handle);
1295 else if (gic == &gic_data[0])
1303 struct gic_chip_data *gic;
1311 gic = &gic_data[0];
1312 gic->raw_dist_base = dist_base;
1313 gic->raw_cpu_base = cpu_base;
1315 __gic_init_bases(gic, NULL);
1318 static void gic_teardown(struct gic_chip_data *gic)
1320 if (WARN_ON(!gic))
1323 if (gic->raw_dist_base)
1324 iounmap(gic->raw_dist_base);
1325 if (gic->raw_cpu_base)
1326 iounmap(gic->raw_cpu_base);
1441 static int gic_of_setup(struct gic_chip_data *gic, struct device_node *node)
1443 if (!gic || !node)
1446 gic->raw_dist_base = of_iomap(node, 0);
1447 if (WARN(!gic->raw_dist_base, "unable to map gic dist registers\n"))
1450 gic->raw_cpu_base = of_iomap(node, 1);
1451 if (WARN(!gic->raw_cpu_base, "unable to map gic cpu registers\n"))
1454 if (of_property_read_u32(node, "cpu-offset", &gic->percpu_offset))
1455 gic->percpu_offset = 0;
1457 gic_enable_of_quirks(node, gic_quirks, gic);
1462 gic_teardown(gic);
1467 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
1471 if (!dev || !dev->of_node || !gic || !irq)
1474 *gic = devm_kzalloc(dev, sizeof(**gic), GFP_KERNEL);
1475 if (!*gic)
1478 gic_init_chip(*gic, dev, dev->of_node->name, false);
1480 ret = gic_of_setup(*gic, dev->of_node);
1484 ret = gic_init_bases(*gic, &dev->of_node->fwnode);
1486 gic_teardown(*gic);
1490 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, *gic);
1522 struct gic_chip_data *gic;
1531 gic = &gic_data[gic_cnt];
1533 ret = gic_of_setup(gic, node);
1541 if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base))
1544 ret = __gic_init_bases(gic, &node->fwnode);
1546 gic_teardown(gic);
1566 IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
1567 IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init);
1568 IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init);
1569 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
1570 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
1571 IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
1576 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
1691 struct gic_chip_data *gic = &gic_data[0];
1702 gic->raw_cpu_base = ioremap(acpi_data.cpu_phys_base, ACPI_GIC_CPU_IF_MEM_SIZE);
1703 if (!gic->raw_cpu_base) {
1709 gic->raw_dist_base = ioremap(dist->base_address,
1711 if (!gic->raw_dist_base) {
1713 gic_teardown(gic);
1731 gic_teardown(gic);
1735 ret = __gic_init_bases(gic, domain_handle);
1739 gic_teardown(gic);