Lines Matching refs:base
12 * associated CPU. The base address of the CPU interface is usually
136 static inline void __iomem *__get_base(union gic_base *base)
139 return raw_cpu_read(*base->percpu_base);
141 return base->common_base;
295 void __iomem *base = gic_dist_base(d);
308 ret = gic_configure_irq(gicirq, type, base + GIC_DIST_CONFIG, NULL);
425 void __iomem *base = gic_data_dist_base(gic);
429 mask = readl_relaxed(base + GIC_DIST_TARGET + i);
442 static bool gic_check_gicv2(void __iomem *base)
444 u32 val = readl_relaxed(base + GIC_CPU_IDENT);
477 void __iomem *base = gic_data_dist_base(gic);
479 writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL);
488 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
490 gic_dist_config(base, gic_irqs, NULL);
492 writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL);
498 void __iomem *base = gic_data_cpu_base(gic);
529 writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK);
1339 static bool gic_check_eoimode(struct device_node *node, void __iomem **base)
1353 if (!gic_check_gicv2(*base))
1372 iounmap(*base);
1373 *base = alt;
1390 iounmap(*base);
1391 *base = alt;
1399 if (!gic_check_gicv2(*base) ||
1400 !gic_check_gicv2(*base + 0xf000))
1404 * Move the base up by 60kB, so that we have a 8kB
1408 *base += 0xf000;
1410 pr_warn("GIC: Adjusting CPU interface base to %pa\n",
1694 /* Collect CPU base addresses */