Lines Matching defs:val
245 enum irqchip_irq_state which, bool val)
251 reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR;
255 reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR;
259 reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET;
271 enum irqchip_irq_state which, bool *val)
275 *val = gic_peek_irq(d, GIC_DIST_PENDING_SET);
279 *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET);
283 *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET);
444 u32 val = readl_relaxed(base + GIC_CPU_IDENT);
445 return (val & 0xff0fff) == 0x02043B;
538 u32 val = 0;
544 val = readl(cpu_base + GIC_CPU_CTRL);
545 val &= ~GICC_ENABLE;
546 writel_relaxed(val, cpu_base + GIC_CPU_CTRL);
788 u32 val;
793 val = readl_relaxed(addr);
794 val &= ~GENMASK(shift + 7, shift);
795 val |= bval << shift;
796 writel_relaxed(val, addr);
937 u32 val, cur_target_mask, active_mask;
961 val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
962 active_mask = val & cur_target_mask;
964 val &= ~active_mask;
965 val |= ror32(active_mask, ror_val);
966 writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4);
984 val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i);
985 if (!val)
987 writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i);
989 if (val & 0xff)
992 val >>= 8;