Lines Matching defs:val
252 u32 val;
259 val = readl_relaxed(rbase + GICR_WAKER);
262 val &= ~GICR_WAKER_ProcessorSleep;
264 val |= GICR_WAKER_ProcessorSleep;
265 writel_relaxed(val, rbase + GICR_WAKER);
268 val = readl_relaxed(rbase + GICR_WAKER);
269 if (!(val & GICR_WAKER_ProcessorSleep))
274 val = readl_relaxed(rbase + GICR_WAKER);
275 if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep))
407 enum irqchip_irq_state which, bool val)
416 reg = val ? GICD_ISPENDR : GICD_ICPENDR;
420 reg = val ? GICD_ISACTIVER : GICD_ICACTIVER;
424 reg = val ? GICD_ICENABLER : GICD_ISENABLER;
436 enum irqchip_irq_state which, bool *val)
443 *val = gic_peek_irq(d, GICD_ISPENDR);
447 *val = gic_peek_irq(d, GICD_ISACTIVER);
451 *val = !gic_peek_irq(d, GICD_ISENABLER);
747 u32 val;
764 val = gic_read_pmr();
768 return val != 0;
776 u32 val;
809 val = GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1;
812 val |= GICD_CTLR_nASSGIreq;
816 writel_relaxed(val, base + GICD_CTLR);
921 u64 val;
924 val = gicr_read_vpendbaser(ptr + SZ_128K + GICR_VPENDBASER);
925 if (val & GICR_VPENDBASER_Valid)
930 val = gicr_read_vpropbaser(ptr + SZ_128K + GICR_VPROPBASER);
931 val &= ~GICR_VPROPBASER_4_1_VALID;
932 gicr_write_vpropbaser(val, ptr + SZ_128K + GICR_VPROPBASER);
1186 u64 val;
1188 val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) |
1195 pr_devel("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val);
1196 gic_write_sgi1r(val);
1253 u64 val;
1273 val = gic_mpidr_to_affinity(cpu_logical_map(cpu));
1275 gic_write_irouter(val, reg);