Lines Matching defs:bgc
73 struct irq_chip_generic *bgc = irq_get_domain_generic_chip(aic5_domain, 0);
77 irqnr = irq_reg_readl(bgc, AT91_AIC5_IVR);
78 irqstat = irq_reg_readl(bgc, AT91_AIC5_ISR);
81 irq_reg_writel(bgc, 0, AT91_AIC5_EOICR);
89 struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);
96 irq_gc_lock(bgc);
100 irq_gc_unlock(bgc);
106 struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);
113 irq_gc_lock(bgc);
117 irq_gc_unlock(bgc);
123 struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);
126 irq_gc_lock(bgc);
127 irq_reg_writel(bgc, d->hwirq, AT91_AIC5_SSR);
128 irq_reg_writel(bgc, 1, AT91_AIC5_ISCR);
129 irq_gc_unlock(bgc);
137 struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);
141 irq_gc_lock(bgc);
142 irq_reg_writel(bgc, d->hwirq, AT91_AIC5_SSR);
143 smr = irq_reg_readl(bgc, AT91_AIC5_SMR);
146 irq_reg_writel(bgc, smr, AT91_AIC5_SMR);
147 irq_gc_unlock(bgc);
159 struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);
166 irq_reg_writel(bgc, i, AT91_AIC5_SSR);
167 smr_cache[i] = irq_reg_readl(bgc, AT91_AIC5_SMR);
170 irq_gc_lock(bgc);
176 irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR);
178 irq_reg_writel(bgc, 1, AT91_AIC5_IECR);
180 irq_reg_writel(bgc, 1, AT91_AIC5_IDCR);
182 irq_gc_unlock(bgc);
189 struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);
194 irq_gc_lock(bgc);
197 irq_reg_writel(bgc, 0xffffffff, AT91_AIC5_SPU);
199 irq_reg_writel(bgc, i, AT91_AIC5_SSR);
200 irq_reg_writel(bgc, i, AT91_AIC5_SVR);
201 irq_reg_writel(bgc, smr_cache[i], AT91_AIC5_SMR);
212 irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR);
214 irq_reg_writel(bgc, 1, AT91_AIC5_IECR);
216 irq_reg_writel(bgc, 1, AT91_AIC5_IDCR);
218 irq_gc_unlock(bgc);
225 struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);
229 irq_gc_lock(bgc);
231 irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR);
232 irq_reg_writel(bgc, 1, AT91_AIC5_IDCR);
233 irq_reg_writel(bgc, 1, AT91_AIC5_ICCR);
235 irq_gc_unlock(bgc);
280 struct irq_chip_generic *bgc = irq_get_domain_generic_chip(d, 0);
285 if (!bgc)
293 irq_gc_lock_irqsave(bgc, flags);
294 irq_reg_writel(bgc, *out_hwirq, AT91_AIC5_SSR);
295 smr = irq_reg_readl(bgc, AT91_AIC5_SMR);
297 irq_reg_writel(bgc, smr, AT91_AIC5_SMR);
298 irq_gc_unlock_irqrestore(bgc, flags);