Lines Matching defs:value
69 static inline void smmu_writel(struct tegra_smmu *smmu, u32 value,
72 writel(value, smmu->regs + offset);
184 u32 value;
190 value = (dma >> 32) & SMMU_PTC_FLUSH_HI_MASK;
192 value = 0;
194 smmu_writel(smmu, value, SMMU_PTC_FLUSH_HI);
197 value = (dma + offset) | SMMU_PTC_FLUSH_TYPE_ADR;
198 smmu_writel(smmu, value, SMMU_PTC_FLUSH);
209 u32 value;
212 value = (asid & 0x3) << 29;
214 value = (asid & 0x7f) << 24;
216 value |= SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_VA_MATCH_ALL;
217 smmu_writel(smmu, value, SMMU_TLB_FLUSH);
224 u32 value;
227 value = (asid & 0x3) << 29;
229 value = (asid & 0x7f) << 24;
231 value |= SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_VA_SECTION(iova);
232 smmu_writel(smmu, value, SMMU_TLB_FLUSH);
239 u32 value;
242 value = (asid & 0x3) << 29;
244 value = (asid & 0x7f) << 24;
246 value |= SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_VA_GROUP(iova);
247 smmu_writel(smmu, value, SMMU_TLB_FLUSH);
363 u32 value;
367 value = smmu_readl(smmu, group->reg);
368 value &= ~SMMU_ASID_MASK;
369 value |= SMMU_ASID_VALUE(asid);
370 value |= SMMU_ASID_ENABLE;
371 smmu_writel(smmu, value, group->reg);
385 value = smmu_readl(smmu, client->smmu.reg);
386 value |= BIT(client->smmu.bit);
387 smmu_writel(smmu, value, client->smmu.reg);
396 u32 value;
400 value = smmu_readl(smmu, group->reg);
401 value &= ~SMMU_ASID_MASK;
402 value |= SMMU_ASID_VALUE(asid);
403 value &= ~SMMU_ASID_ENABLE;
404 smmu_writel(smmu, value, group->reg);
413 value = smmu_readl(smmu, client->smmu.reg);
414 value &= ~BIT(client->smmu.bit);
415 smmu_writel(smmu, value, client->smmu.reg);
422 u32 value;
449 value = SMMU_PTB_DATA_VALUE(as->pd_dma, as->attr);
450 smmu_writel(smmu, value, SMMU_PTB_DATA);
537 u32 value)
545 pd[pd_index] = value;
1009 u32 value;
1019 value = smmu_readl(smmu, group->reg);
1021 if (value & SMMU_ASID_ENABLE)
1026 asid = value & SMMU_ASID_MASK;
1041 u32 value;
1050 value = smmu_readl(smmu, client->smmu.reg);
1052 if (value & BIT(client->smmu.bit))
1088 u32 value;
1097 * value. However the IOMMU registration process will attempt to add
1127 value = SMMU_PTC_CONFIG_ENABLE | SMMU_PTC_CONFIG_INDEX_MAP(0x3f);
1130 value |= SMMU_PTC_CONFIG_REQ_LIMIT(8);
1132 smmu_writel(smmu, value, SMMU_PTC_CONFIG);
1134 value = SMMU_TLB_CONFIG_HIT_UNDER_MISS |
1138 value |= SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION;
1140 smmu_writel(smmu, value, SMMU_TLB_CONFIG);