Lines Matching defs:base
130 data->base + REG_MMU_INV_SEL);
131 writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE);
142 data->base + REG_MMU_INV_SEL);
144 data->base + REG_MMU_INVLD_START_A);
146 data->base + REG_MMU_INVLD_END_A);
147 writel_relaxed(F_MMU_INV_RANGE, data->base + REG_MMU_INVALIDATE);
149 ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE,
157 writel_relaxed(0, data->base + REG_MMU_CPE_DONE);
168 int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST);
169 fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA);
172 fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA);
173 regval = readl_relaxed(data->base + REG_MMU_INT_ID);
189 regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL);
191 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL);
232 writel(dom->pgt_pa, data->base + REG_MMU_PT_BASE_ADDR);
489 writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
499 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL);
503 data->base + REG_MMU_IVRP_PADDR);
505 writel_relaxed(F_MMU_DCM_ON, data->base + REG_MMU_DCM);
509 writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR);
569 data->base = devm_ioremap_resource(dev, res);
570 if (IS_ERR(data->base))
571 return PTR_ERR(data->base);
671 void __iomem *base = data->base;
673 reg->standard_axi_mode = readl_relaxed(base +
675 reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM);
676 reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
677 reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL);
685 void __iomem *base = data->base;
687 writel_relaxed(data->m4u_dom->pgt_pa, base + REG_MMU_PT_BASE_ADDR);
689 base + REG_MMU_STANDARD_AXI_MODE);
690 writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM);
691 writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
692 writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL);
693 writel_relaxed(data->protect_base, base + REG_MMU_IVRP_PADDR);