Lines Matching defs:base
191 data->base + data->plat_data->inv_sel_reg);
192 writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE);
208 data->base + data->plat_data->inv_sel_reg);
210 writel_relaxed(iova, data->base + REG_MMU_INVLD_START_A);
212 data->base + REG_MMU_INVLD_END_A);
214 data->base + REG_MMU_INVALIDATE);
217 ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE,
225 writel_relaxed(0, data->base + REG_MMU_CPE_DONE);
256 int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST1);
258 regval = readl_relaxed(data->base + REG_MMU0_INT_ID);
259 fault_iova = readl_relaxed(data->base + REG_MMU0_FAULT_VA);
260 fault_pa = readl_relaxed(data->base + REG_MMU0_INVLD_PA);
262 regval = readl_relaxed(data->base + REG_MMU1_INT_ID);
263 fault_iova = readl_relaxed(data->base + REG_MMU1_FAULT_VA);
264 fault_pa = readl_relaxed(data->base + REG_MMU1_INVLD_PA);
287 regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL0);
289 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0);
394 /* Update the pgtable base address register of the M4U HW */
398 data->base + REG_MMU_PT_BASE_ADDR);
566 regval = readl_relaxed(data->base + REG_MMU_CTRL_REG);
569 writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
577 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0);
586 writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL);
593 writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR);
602 writel_relaxed(regval, data->base + REG_MMU_VLD_PA_RNG);
604 writel_relaxed(0, data->base + REG_MMU_DCM_DIS);
607 regval = readl_relaxed(data->base + REG_MMU_WR_LEN_CTRL);
609 writel_relaxed(regval, data->base + REG_MMU_WR_LEN_CTRL);
616 regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL);
621 writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL);
625 writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR);
688 data->base = devm_ioremap_resource(dev, res);
689 if (IS_ERR(data->base))
690 return PTR_ERR(data->base);
783 void __iomem *base = data->base;
785 reg->wr_len_ctrl = readl_relaxed(base + REG_MMU_WR_LEN_CTRL);
786 reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL);
787 reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS);
788 reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
789 reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL0);
790 reg->int_main_control = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL);
791 reg->ivrp_paddr = readl_relaxed(base + REG_MMU_IVRP_PADDR);
792 reg->vld_pa_rng = readl_relaxed(base + REG_MMU_VLD_PA_RNG);
802 void __iomem *base = data->base;
810 writel_relaxed(reg->wr_len_ctrl, base + REG_MMU_WR_LEN_CTRL);
811 writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL);
812 writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS);
813 writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
814 writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0);
815 writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL);
816 writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR);
817 writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG);
820 base + REG_MMU_PT_BASE_ADDR);