Lines Matching refs:iommu
18 #include <linux/iommu.h>
55 static int __enable_clocks(struct msm_iommu_dev *iommu)
59 ret = clk_enable(iommu->pclk);
63 if (iommu->clk) {
64 ret = clk_enable(iommu->clk);
66 clk_disable(iommu->pclk);
72 static void __disable_clocks(struct msm_iommu_dev *iommu)
74 if (iommu->clk)
75 clk_disable(iommu->clk);
76 clk_disable(iommu->pclk);
121 struct msm_iommu_dev *iommu = NULL;
125 list_for_each_entry(iommu, &priv->list_attached, dom_node) {
126 ret = __enable_clocks(iommu);
130 list_for_each_entry(master, &iommu->ctx_list, list)
131 SET_CTX_TLBIALL(iommu->base, master->num, 0);
133 __disable_clocks(iommu);
143 struct msm_iommu_dev *iommu = NULL;
148 list_for_each_entry(iommu, &priv->list_attached, dom_node) {
149 ret = __enable_clocks(iommu);
153 list_for_each_entry(master, &iommu->ctx_list, list) {
157 iova |= GET_CONTEXTIDR_ASID(iommu->base,
159 SET_TLBIVA(iommu->base, master->num, iova);
164 __disable_clocks(iommu);
214 static void config_mids(struct msm_iommu_dev *iommu,
223 SET_M2VCBR_N(iommu->base, mid, 0);
224 SET_CBACR_N(iommu->base, ctx, 0);
227 SET_VMID(iommu->base, mid, 0);
230 SET_CBNDX(iommu->base, mid, ctx);
233 SET_CBVMID(iommu->base, ctx, 0);
236 SET_CONTEXTIDR_ASID(iommu->base, ctx, ctx);
239 SET_NSCFG(iommu->base, mid, 3);
375 struct msm_iommu_dev *iommu, *ret = NULL;
378 list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) {
379 master = list_first_entry(&iommu->ctx_list,
383 ret = iommu;
393 struct msm_iommu_dev *iommu;
397 iommu = find_iommu_for_dev(dev);
400 if (!iommu)
403 return &iommu->iommu;
414 struct msm_iommu_dev *iommu;
422 list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) {
423 master = list_first_entry(&iommu->ctx_list,
427 ret = __enable_clocks(iommu);
431 list_for_each_entry(master, &iommu->ctx_list, list) {
438 msm_iommu_alloc_ctx(iommu->context_map,
439 0, iommu->ncb);
444 config_mids(iommu, master);
445 __program_context(iommu->base, master->num,
448 __disable_clocks(iommu);
449 list_add(&iommu->dom_node, &priv->list_attached);
464 struct msm_iommu_dev *iommu;
471 list_for_each_entry(iommu, &priv->list_attached, dom_node) {
472 ret = __enable_clocks(iommu);
476 list_for_each_entry(master, &iommu->ctx_list, list) {
477 msm_iommu_free_ctx(iommu->context_map, master->num);
478 __reset_context(iommu->base, master->num);
480 __disable_clocks(iommu);
517 struct msm_iommu_dev *iommu;
526 iommu = list_first_entry(&priv->list_attached,
529 if (list_empty(&iommu->ctx_list))
532 master = list_first_entry(&iommu->ctx_list,
537 ret = __enable_clocks(iommu);
542 SET_CTX_TLBIALL(iommu->base, master->num, 0);
543 SET_V2PPR(iommu->base, master->num, va & V2Pxx_VA);
545 par = GET_PAR(iommu->base, master->num);
548 if (GET_NOFAULT_SS(iommu->base, master->num))
553 if (GET_FAULT(iommu->base, master->num))
556 __disable_clocks(iommu);
593 struct msm_iommu_dev **iommu,
599 if (list_empty(&(*iommu)->ctx_list)) {
602 list_add(&master->list, &(*iommu)->ctx_list);
619 struct msm_iommu_dev *iommu = NULL, *iter;
626 iommu = iter;
631 if (!iommu) {
636 insert_iommu_master(dev, &iommu, spec);
645 struct msm_iommu_dev *iommu = dev_id;
651 if (!iommu) {
657 pr_err("base = %08x\n", (unsigned int)iommu->base);
659 ret = __enable_clocks(iommu);
663 for (i = 0; i < iommu->ncb; i++) {
664 fsr = GET_FSR(iommu->base, i);
668 print_ctx_regs(iommu->base, i);
669 SET_FSR(iommu->base, i, 0x4000000F);
672 __disable_clocks(iommu);
689 * taken care when the iommu client does a writel before
705 struct msm_iommu_dev *iommu;
708 iommu = devm_kzalloc(&pdev->dev, sizeof(*iommu), GFP_KERNEL);
709 if (!iommu)
712 iommu->dev = &pdev->dev;
713 INIT_LIST_HEAD(&iommu->ctx_list);
715 iommu->pclk = devm_clk_get(iommu->dev, "smmu_pclk");
716 if (IS_ERR(iommu->pclk)) {
717 dev_err(iommu->dev, "could not get smmu_pclk\n");
718 return PTR_ERR(iommu->pclk);
721 ret = clk_prepare(iommu->pclk);
723 dev_err(iommu->dev, "could not prepare smmu_pclk\n");
727 iommu->clk = devm_clk_get(iommu->dev, "iommu_clk");
728 if (IS_ERR(iommu->clk)) {
729 dev_err(iommu->dev, "could not get iommu_clk\n");
730 clk_unprepare(iommu->pclk);
731 return PTR_ERR(iommu->clk);
734 ret = clk_prepare(iommu->clk);
736 dev_err(iommu->dev, "could not prepare iommu_clk\n");
737 clk_unprepare(iommu->pclk);
742 iommu->base = devm_ioremap_resource(iommu->dev, r);
743 if (IS_ERR(iommu->base)) {
744 dev_err(iommu->dev, "could not get iommu base\n");
745 ret = PTR_ERR(iommu->base);
750 iommu->irq = platform_get_irq(pdev, 0);
751 if (iommu->irq < 0) {
756 ret = of_property_read_u32(iommu->dev->of_node, "qcom,ncb", &val);
758 dev_err(iommu->dev, "could not get ncb\n");
761 iommu->ncb = val;
763 msm_iommu_reset(iommu->base, iommu->ncb);
764 SET_M(iommu->base, 0, 1);
765 SET_PAR(iommu->base, 0, 0);
766 SET_V2PCFG(iommu->base, 0, 1);
767 SET_V2PPR(iommu->base, 0, 0);
768 par = GET_PAR(iommu->base, 0);
769 SET_V2PCFG(iommu->base, 0, 0);
770 SET_M(iommu->base, 0, 0);
778 ret = devm_request_threaded_irq(iommu->dev, iommu->irq, NULL,
782 iommu);
784 pr_err("Request IRQ %d failed with ret=%d\n", iommu->irq, ret);
788 list_add(&iommu->dev_node, &qcom_iommu_devices);
790 ret = iommu_device_sysfs_add(&iommu->iommu, iommu->dev, NULL,
797 iommu_device_set_ops(&iommu->iommu, &msm_iommu_ops);
798 iommu_device_set_fwnode(&iommu->iommu, &pdev->dev.of_node->fwnode);
800 ret = iommu_device_register(&iommu->iommu);
809 iommu->base, iommu->irq, iommu->ncb);
813 clk_unprepare(iommu->clk);
814 clk_unprepare(iommu->pclk);
819 { .compatible = "qcom,apq8064-iommu" },
825 struct msm_iommu_dev *iommu = platform_get_drvdata(pdev);
827 clk_unprepare(iommu->clk);
828 clk_unprepare(iommu->pclk);