Lines Matching refs:base
79 static void msm_iommu_reset(void __iomem *base, int ncb)
83 SET_RPUE(base, 0);
84 SET_RPUEIE(base, 0);
85 SET_ESRRESTORE(base, 0);
86 SET_TBE(base, 0);
87 SET_CR(base, 0);
88 SET_SPDMBE(base, 0);
89 SET_TESTBUSCR(base, 0);
90 SET_TLBRSW(base, 0);
91 SET_GLOBAL_TLBIALL(base, 0);
92 SET_RPU_ACR(base, 0);
93 SET_TLBLKCRWE(base, 1);
96 SET_BPRCOSH(base, ctx, 0);
97 SET_BPRCISH(base, ctx, 0);
98 SET_BPRCNSH(base, ctx, 0);
99 SET_BPSHCFG(base, ctx, 0);
100 SET_BPMTCFG(base, ctx, 0);
101 SET_ACTLR(base, ctx, 0);
102 SET_SCTLR(base, ctx, 0);
103 SET_FSRRESTORE(base, ctx, 0);
104 SET_TTBR0(base, ctx, 0);
105 SET_TTBR1(base, ctx, 0);
106 SET_TTBCR(base, ctx, 0);
107 SET_BFBCR(base, ctx, 0);
108 SET_PAR(base, ctx, 0);
109 SET_FAR(base, ctx, 0);
110 SET_CTX_TLBIALL(base, ctx, 0);
111 SET_TLBFLPTER(base, ctx, 0);
112 SET_TLBSLPTER(base, ctx, 0);
113 SET_TLBLKCR(base, ctx, 0);
114 SET_CONTEXTIDR(base, ctx, 0);
131 SET_CTX_TLBIALL(iommu->base, master->num, 0);
157 iova |= GET_CONTEXTIDR_ASID(iommu->base,
159 SET_TLBIVA(iommu->base, master->num, iova);
223 SET_M2VCBR_N(iommu->base, mid, 0);
224 SET_CBACR_N(iommu->base, ctx, 0);
227 SET_VMID(iommu->base, mid, 0);
230 SET_CBNDX(iommu->base, mid, ctx);
233 SET_CBVMID(iommu->base, ctx, 0);
236 SET_CONTEXTIDR_ASID(iommu->base, ctx, ctx);
239 SET_NSCFG(iommu->base, mid, 3);
243 static void __reset_context(void __iomem *base, int ctx)
245 SET_BPRCOSH(base, ctx, 0);
246 SET_BPRCISH(base, ctx, 0);
247 SET_BPRCNSH(base, ctx, 0);
248 SET_BPSHCFG(base, ctx, 0);
249 SET_BPMTCFG(base, ctx, 0);
250 SET_ACTLR(base, ctx, 0);
251 SET_SCTLR(base, ctx, 0);
252 SET_FSRRESTORE(base, ctx, 0);
253 SET_TTBR0(base, ctx, 0);
254 SET_TTBR1(base, ctx, 0);
255 SET_TTBCR(base, ctx, 0);
256 SET_BFBCR(base, ctx, 0);
257 SET_PAR(base, ctx, 0);
258 SET_FAR(base, ctx, 0);
259 SET_CTX_TLBIALL(base, ctx, 0);
260 SET_TLBFLPTER(base, ctx, 0);
261 SET_TLBSLPTER(base, ctx, 0);
262 SET_TLBLKCR(base, ctx, 0);
265 static void __program_context(void __iomem *base, int ctx,
268 __reset_context(base, ctx);
271 SET_TRE(base, ctx, 1);
272 SET_AFE(base, ctx, 1);
276 SET_TLBMCFG(base, ctx, 0x3);
279 SET_V2PCFG(base, ctx, 0x3);
281 SET_TTBCR(base, ctx, priv->cfg.arm_v7s_cfg.tcr);
282 SET_TTBR0(base, ctx, priv->cfg.arm_v7s_cfg.ttbr);
283 SET_TTBR1(base, ctx, 0);
286 SET_PRRR(base, ctx, priv->cfg.arm_v7s_cfg.prrr);
287 SET_NMRR(base, ctx, priv->cfg.arm_v7s_cfg.nmrr);
290 SET_CTX_TLBIALL(base, ctx, 0);
293 SET_IRPTNDX(base, ctx, 0);
296 SET_CFEIE(base, ctx, 1);
299 SET_CFCFG(base, ctx, 1);
302 SET_RCISH(base, ctx, 1);
303 SET_RCOSH(base, ctx, 1);
304 SET_RCNSH(base, ctx, 1);
307 SET_BFBDFE(base, ctx, 1);
310 SET_M(base, ctx, 1);
445 __program_context(iommu->base, master->num,
478 __reset_context(iommu->base, master->num);
542 SET_CTX_TLBIALL(iommu->base, master->num, 0);
543 SET_V2PPR(iommu->base, master->num, va & V2Pxx_VA);
545 par = GET_PAR(iommu->base, master->num);
548 if (GET_NOFAULT_SS(iommu->base, master->num))
553 if (GET_FAULT(iommu->base, master->num))
567 static void print_ctx_regs(void __iomem *base, int ctx)
569 unsigned int fsr = GET_FSR(base, ctx);
571 GET_FAR(base, ctx), GET_PAR(base, ctx));
585 GET_FSYNR0(base, ctx), GET_FSYNR1(base, ctx));
587 GET_TTBR0(base, ctx), GET_TTBR1(base, ctx));
589 GET_SCTLR(base, ctx), GET_ACTLR(base, ctx));
657 pr_err("base = %08x\n", (unsigned int)iommu->base);
664 fsr = GET_FSR(iommu->base, i);
668 print_ctx_regs(iommu->base, i);
669 SET_FSR(iommu->base, i, 0x4000000F);
742 iommu->base = devm_ioremap_resource(iommu->dev, r);
743 if (IS_ERR(iommu->base)) {
744 dev_err(iommu->dev, "could not get iommu base\n");
745 ret = PTR_ERR(iommu->base);
763 msm_iommu_reset(iommu->base, iommu->ncb);
764 SET_M(iommu->base, 0, 1);
765 SET_PAR(iommu->base, 0, 0);
766 SET_V2PCFG(iommu->base, 0, 1);
767 SET_V2PPR(iommu->base, 0, 0);
768 par = GET_PAR(iommu->base, 0);
769 SET_V2PCFG(iommu->base, 0, 0);
770 SET_M(iommu->base, 0, 0);
809 iommu->base, iommu->irq, iommu->ncb);