Lines Matching defs:sfrbase
265 void __iomem *sfrbase; /* our registers */
288 writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL);
295 writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL);
296 while ((i > 0) && !(readl(data->sfrbase + REG_MMU_STATUS) & 1))
299 if (!(readl(data->sfrbase + REG_MMU_STATUS) & 1)) {
310 writel(0x1, data->sfrbase + REG_MMU_FLUSH);
312 writel(0x1, data->sfrbase + REG_V5_MMU_FLUSH_ALL);
323 data->sfrbase + REG_MMU_FLUSH_ENTRY);
329 data->sfrbase + REG_V5_MMU_FLUSH_ENTRY);
332 data->sfrbase + REG_V5_MMU_FLUSH_START);
334 data->sfrbase + REG_V5_MMU_FLUSH_END);
335 writel(1, data->sfrbase + REG_V5_MMU_FLUSH_RANGE);
343 writel(pgd, data->sfrbase + REG_PT_BASE_ADDR);
346 data->sfrbase + REG_V5_PT_BASE_PFN);
373 ver = readl(data->sfrbase + REG_MMU_VERSION);
432 itype = __ffs(readl(data->sfrbase + reg_status));
440 fault_addr = readl(data->sfrbase + finfo->addr_reg);
449 writel(1 << itype, data->sfrbase + reg_clear);
467 writel(CTRL_DISABLE, data->sfrbase + REG_MMU_CTRL);
468 writel(0, data->sfrbase + REG_MMU_CFG);
488 writel(cfg, data->sfrbase + REG_MMU_CFG);
498 writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL);
501 writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL);
581 data->sfrbase = devm_ioremap_resource(dev, res);
582 if (IS_ERR(data->sfrbase))
583 return PTR_ERR(data->sfrbase);