Lines Matching defs:enables
3032 u32 reg, enables;
3071 enables = CR0_CMDQEN;
3072 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0,
3101 enables |= CR0_EVTQEN;
3102 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0,
3118 enables |= CR0_PRIQEN;
3119 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0,
3128 enables |= CR0_ATSCHK;
3129 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0,
3144 enables &= ~(CR0_EVTQEN | CR0_PRIQEN);
3148 enables |= CR0_SMMUEN;
3154 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0,