Lines Matching refs:pasid
580 u32 pasid;
585 pasid = (event[0] & EVENT_DOMID_MASK_HI) |
601 amd_iommu_report_page_fault(devid, pasid, address, flags);
607 dev_err(dev, "Event logged [ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
609 pasid, address, flags);
619 dev_err(dev, "Event logged [PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x pasid=0x%04x address=0x%llx flags=0x%04x]\n",
621 pasid, address, flags);
637 dev_err(dev, "Event logged [INVALID_DEVICE_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
639 pasid, address, flags);
648 pasid = PPR_PASID(*((u64 *)__evt));
650 dev_err(dev, "Event logged [INVALID_PPR_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x tag=0x%03x]\n",
652 pasid, address, flags, tag);
687 fault.pasid = PPR_PASID(raw[0]);
1000 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, u32 pasid,
1007 cmd->data[0] = pasid;
1018 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, u32 pasid,
1026 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
1029 cmd->data[1] |= (pasid & 0xff) << 16;
1038 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, u32 pasid,
1045 cmd->data[1] = pasid;
2879 static int __flush_pasid(struct protection_domain *domain, u32 pasid,
2889 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
2922 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
2940 static int __amd_iommu_flush_page(struct protection_domain *domain, u32 pasid,
2943 return __flush_pasid(domain, pasid, address, false);
2946 int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid,
2954 ret = __amd_iommu_flush_page(domain, pasid, address);
2961 static int __amd_iommu_flush_tlb(struct protection_domain *domain, u32 pasid)
2963 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
2967 int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid)
2974 ret = __amd_iommu_flush_tlb(domain, pasid);
2981 static u64 *__get_gcr3_pte(u64 *root, int level, u32 pasid, bool alloc)
2988 index = (pasid >> (9 * level)) & 0x1ff;
3013 static int __set_gcr3(struct protection_domain *domain, u32 pasid,
3023 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3029 return __amd_iommu_flush_tlb(domain, pasid);
3032 static int __clear_gcr3(struct protection_domain *domain, u32 pasid)
3041 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3047 return __amd_iommu_flush_tlb(domain, pasid);
3050 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, u32 pasid,
3058 ret = __set_gcr3(domain, pasid, cr3);
3065 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, u32 pasid)
3072 ret = __clear_gcr3(domain, pasid);
3079 int amd_iommu_complete_ppr(struct pci_dev *pdev, u32 pasid,
3089 build_complete_ppr(&cmd, dev_data->devid, pasid, status,