Lines Matching defs:root
160 pgtable->root = (u64 *)(pt_root & PAGE_MASK);
164 static void amd_iommu_domain_set_pt_root(struct protection_domain *domain, u64 root)
166 atomic64_set(&domain->pt_root, root);
175 u64 *root, int mode)
181 pt_root |= (u64)root;
1450 static struct page *free_sub_pt(unsigned long root, int mode,
1458 freelist = free_pt_page(root, freelist);
1461 freelist = free_pt_l2(root, freelist);
1464 freelist = free_pt_l3(root, freelist);
1467 freelist = free_pt_l4(root, freelist);
1470 freelist = free_pt_l5(root, freelist);
1473 freelist = free_pt_l6(root, freelist);
1485 unsigned long root;
1493 root = (unsigned long)pgtable->root;
1494 freelist = free_sub_pt(root, pgtable->mode, freelist);
1528 *pte = PM_LEVEL_PDE(pgtable.mode, iommu_virt_to_phys(pgtable.root));
1530 pgtable.root = pte;
1536 * Device Table needs to be updated and flushed before the new root can
1580 pte = &pgtable.root[PM_LEVEL_INDEX(level, address)];
1668 pte = &pgtable.root[PM_LEVEL_INDEX(level, address)];
1917 pte_root = iommu_virt_to_phys(pgtable->root);
2981 static u64 *__get_gcr3_pte(u64 *root, int level, u32 pasid, bool alloc)
2989 pte = &root[index];
2998 root = (void *)get_zeroed_page(GFP_ATOMIC);
2999 if (root == NULL)
3002 *pte = iommu_virt_to_phys(root) | GCR3_VALID;
3005 root = iommu_phys_to_virt(*pte & PAGE_MASK);