Lines Matching defs:page
51 /* IO virtual address start page frame number */
62 * This bitmap is used to advertise the page sizes our hardware support
64 * physically contiguous memory regions it is mapping into page sizes
949 * If we have to flush more than one page, flush all
963 if (s) /* size bit - we flush more than one 4kb page */
980 * If we have to flush more than one page, flush all
1306 * page. Otherwise it flushes the whole TLB of the IOMMU.
1395 * The functions below are used the create the page table mappings for
1400 static void free_page_list(struct page *freelist)
1409 static struct page *free_pt_page(unsigned long pt, struct page *freelist)
1411 struct page *p = virt_to_page((void *)pt);
1419 static struct page *free_pt_##LVL (unsigned long __pt, struct page *freelist) \
1450 static struct page *free_sub_pt(unsigned long root, int mode,
1451 struct page *freelist)
1484 struct page *freelist = NULL;
1500 * This function is used to add another level to an IO page table. Adding
1560 u64 *pte, *page;
1569 * page-table.
1615 page = (u64 *)get_zeroed_page(gfp);
1617 if (!page)
1620 __npte = PM_LEVEL_PDE(level, iommu_virt_to_phys(page));
1624 free_page((unsigned long)page);
1704 static struct page *free_clear_pte(u64 *pte, u64 pteval, struct page *freelist)
1725 * address space. It allocates the page table pages if necessary.
1727 * supporting all features of AMD IOMMU page tables like level skipping
1737 struct page *freelist = NULL;
1837 * about domains is the page table mapping the DMA address space they
2820 /* Remove page-table from domain */