Lines Matching defs:cspec
902 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
904 return readq(&dd->cspec->cregbase[regno]);
911 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
913 return readl(&dd->cspec->cregbase[regno]);
1521 if ((op & QIB_SDMA_SENDCTRL_OP_DRAIN) && ppd->dd->cspec->r1)
1666 errs &= dd->cspec->errormask;
1667 msg = dd->cspec->emsgbuf;
1672 qib_7322_handle_hwerrors(dd, msg, sizeof(dd->cspec->emsgbuf));
1694 err_decode(msg, sizeof(dd->cspec->emsgbuf), errs & ~mask,
1741 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
1804 if (!ppd->dd->cspec->r1)
1825 if (!ppd->dd->cspec->r1 &&
1840 ppd->dd->cspec->r1 ?
2018 qib_write_kreg(dd, kr_intmask, dd->cspec->int_enable_mask);
2021 if (dd->cspec->num_msix_entries) {
2074 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
2118 hwerrs &= dd->cspec->hwerrmask;
2133 dd->cspec->stay_in_freeze) {
2153 dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed);
2154 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
2225 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
2231 dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask);
2248 dd->cspec->errormask |= QIB_E_SPIOARMLAUNCH;
2250 dd->cspec->errormask &= ~QIB_E_SPIOARMLAUNCH;
2251 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
2501 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
2504 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
2532 if (ppd->dd->cspec->r1)
2642 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
2643 extctl = dd->cspec->extctrl & (ppd->port == 1 ?
2657 dd->cspec->extctrl = extctl;
2658 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
2659 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
2683 dd->cspec->dca_ctrl = 0;
2685 dd->cspec->dca_ctrl);
2695 struct qib_chip_specific *cspec = dd->cspec;
2699 if (cspec->rhdr_cpu[rcd->ctxt] != cpu) {
2702 cspec->rhdr_cpu[rcd->ctxt] = cpu;
2704 cspec->dca_rcvhdr_ctrl[rmp->shadow_inx] &= rmp->mask;
2705 cspec->dca_rcvhdr_ctrl[rmp->shadow_inx] |=
2709 (long long) cspec->dca_rcvhdr_ctrl[rmp->shadow_inx]);
2711 cspec->dca_rcvhdr_ctrl[rmp->shadow_inx]);
2712 cspec->dca_ctrl |= SYM_MASK(DCACtrlA, RcvHdrqDCAEnable);
2713 qib_write_kreg(dd, KREG_IDX(DCACtrlA), cspec->dca_ctrl);
2720 struct qib_chip_specific *cspec = dd->cspec;
2725 if (cspec->sdma_cpu[pidx] != cpu) {
2726 cspec->sdma_cpu[pidx] = cpu;
2727 cspec->dca_rcvhdr_ctrl[4] &= ~(ppd->hw_pidx ?
2730 cspec->dca_rcvhdr_ctrl[4] |=
2737 (long long) cspec->dca_rcvhdr_ctrl[4]);
2739 cspec->dca_rcvhdr_ctrl[4]);
2740 cspec->dca_ctrl |= ppd->hw_pidx ?
2743 qib_write_kreg(dd, KREG_IDX(DCACtrlA), cspec->dca_ctrl);
2749 struct qib_chip_specific *cspec = dd->cspec;
2752 for (i = 0; i < ARRAY_SIZE(cspec->rhdr_cpu); i++)
2753 cspec->rhdr_cpu[i] = -1;
2754 for (i = 0; i < ARRAY_SIZE(cspec->sdma_cpu); i++)
2755 cspec->sdma_cpu[i] = -1;
2756 cspec->dca_rcvhdr_ctrl[0] =
2761 cspec->dca_rcvhdr_ctrl[1] =
2766 cspec->dca_rcvhdr_ctrl[2] =
2771 cspec->dca_rcvhdr_ctrl[3] =
2776 cspec->dca_rcvhdr_ctrl[4] =
2779 for (i = 0; i < ARRAY_SIZE(cspec->sdma_cpu); i++)
2781 cspec->dca_rcvhdr_ctrl[i]);
2782 for (i = 0; i < cspec->num_msix_entries; i++)
2830 dd->cspec->main_int_mask = ~0ULL;
2832 for (i = 0; i < dd->cspec->num_msix_entries; i++) {
2834 if (dd->cspec->msix_entries[i].arg) {
2840 free_cpumask_var(dd->cspec->msix_entries[i].mask);
2842 dd->cspec->msix_entries[i].arg);
2847 if (!dd->cspec->num_msix_entries)
2850 dd->cspec->num_msix_entries = 0;
2868 dd->cspec->dca_ctrl = 0;
2869 qib_write_kreg(dd, KREG_IDX(DCACtrlA), dd->cspec->dca_ctrl);
2874 kfree(dd->cspec->cntrs);
2875 kfree(dd->cspec->sendchkenable);
2876 kfree(dd->cspec->sendgrhchk);
2877 kfree(dd->cspec->sendibchk);
2878 kfree(dd->cspec->msix_entries);
2886 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
2887 dd->cspec->gpio_mask &= ~mask;
2888 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
2889 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
2946 qib_write_kreg(dd, kr_intmask, (dd->cspec->int_enable_mask & ~kills));
2987 if (gpiostatus & dd->cspec->gpio_mask & mask) {
3009 dd->cspec->gpio_mask &= ~gpio_irq;
3010 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
3041 u32 timeout = dd->cspec->rcvavail_timeout[rcd->ctxt];
3054 dd->cspec->rcvavail_timeout[rcd->ctxt] = timeout;
3097 istat &= dd->cspec->main_int_mask;
3328 if (!dd->cspec->msix_entries[msixnum].dca)
3334 dd->cspec->msix_entries[msixnum].notifier = NULL;
3339 struct qib_msix_entry *m = &dd->cspec->msix_entries[msixnum];
3407 if (!dd->cspec->num_msix_entries) {
3419 dd->cspec->main_int_mask = ~0ULL;
3440 for (i = 0; msixnum < dd->cspec->num_msix_entries; i++) {
3500 dd->cspec->msix_entries[msixnum].arg = arg;
3502 dd->cspec->msix_entries[msixnum].dca = dca;
3503 dd->cspec->msix_entries[msixnum].rcv =
3517 &dd->cspec->msix_entries[msixnum].mask,
3521 dd->cspec->msix_entries[msixnum].mask);
3528 dd->cspec->msix_entries[msixnum].mask);
3532 dd->cspec->msix_entries[msixnum].mask);
3539 dd->cspec->main_int_mask = mask;
3639 msix_entries = dd->cspec->num_msix_entries;
3648 msix_vecsave = kmalloc_array(2 * dd->cspec->num_msix_entries,
3741 dd->cspec->num_msix_entries = msix_entries;
3876 if (rcd->dd->cspec->r1)
3902 dd->cspec->numctxts = nchipctxts;
3935 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
3950 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
3953 dd->cspec->rcvegrcnt = qib_read_kreg32(dd, kr_rcvegrcnt);
3955 dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt, qib_rcvhdrcnt);
3957 dd->rcvhdrcnt = 2 * max(dd->cspec->rcvegrcnt,
4301 if (ppd->dd->cspec->r1) {
4487 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
4589 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
5001 dd->cspec->ncntrs = i;
5004 dd->cspec->cntrnamelen = sizeof(cntr7322names) - 1;
5006 dd->cspec->cntrnamelen = 1 + s - cntr7322names;
5007 dd->cspec->cntrs = kmalloc_array(dd->cspec->ncntrs, sizeof(u64),
5012 dd->cspec->nportcntrs = i - 1;
5013 dd->cspec->portcntrnamelen = sizeof(portcntr7322names) - 1;
5016 kmalloc_array(dd->cspec->nportcntrs, sizeof(u64),
5027 ret = dd->cspec->cntrnamelen;
5033 u64 *cntr = dd->cspec->cntrs;
5036 ret = dd->cspec->ncntrs * sizeof(u64);
5043 for (i = 0; i < dd->cspec->ncntrs; i++)
5062 ret = dd->cspec->portcntrnamelen;
5072 ret = dd->cspec->nportcntrs * sizeof(u64);
5079 for (i = 0; i < dd->cspec->nportcntrs; i++) {
5148 ppd->dd->cspec->r1 ?
5162 if (!dd->cspec->num_msix_entries)
5193 dd->cspec->hwerrmask & ~HWE_MASK(statusValidNoEop));
5205 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
5651 if (ppd->dd->cspec->r1 && ppd->cpspec->ipg_tries <= 10)
5703 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
5704 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe));
5705 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe));
5706 new_out = (dd->cspec->gpio_out & ~mask) | out;
5708 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
5710 dd->cspec->gpio_out = new_out;
5711 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
5792 * The chip base addresses in cspec and cpspec have to be set
5802 dd->cspec->cregbase = (u64 __iomem *)(cregbase +
5978 if (!ret && !ppd->dd->cspec->r1) {
6026 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
6027 dd->cspec->extctrl |= (mod_prs_bit << SYM_LSB(EXTCtrl, GPIOInvert));
6028 dd->cspec->gpio_mask |= mod_prs_bit;
6029 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
6030 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
6031 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
6270 if (ppd->dd->cspec->r1)
6301 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
6303 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
6339 dd->cspec->rcvavail_timeout[i] = rcv_int_timeout;
6379 dd->cspec = (struct qib_chip_specific *)(ppd + 2);
6381 ppd[0].cpspec = (struct qib_chippport_specific *)(dd->cspec + 1);
6386 spin_lock_init(&dd->cspec->rcvmod_lock);
6387 spin_lock_init(&dd->cspec->gpio_lock);
6402 dd->cspec->r1 = dd->minrev == 1;
6411 dd->cspec->sendchkenable =
6412 kmalloc_array(sbufcnt, sizeof(*dd->cspec->sendchkenable),
6414 dd->cspec->sendgrhchk =
6415 kmalloc_array(sbufcnt, sizeof(*dd->cspec->sendgrhchk),
6417 dd->cspec->sendibchk =
6418 kmalloc_array(sbufcnt, sizeof(*dd->cspec->sendibchk),
6420 if (!dd->cspec->sendchkenable || !dd->cspec->sendgrhchk ||
6421 !dd->cspec->sendibchk) {
6453 dd->cspec->int_enable_mask = QIB_I_BITSEXTANT;
6455 dd->cspec->hwerrmask = ~0ULL;
6458 dd->cspec->hwerrmask &=
6476 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask,
6480 dd->cspec->int_enable_mask &= ~(
6491 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask,
6495 dd->cspec->int_enable_mask &= ~(
6556 if (ppd->dd->cspec->r1)
6665 dd->cspec->sdmabufcnt = dd->piobcnt4k;
6668 dd->cspec->sdmabufcnt = 0;
6671 dd->cspec->lastbuf_for_pio = dd->piobcnt2k + dd->piobcnt4k -
6672 dd->cspec->sdmabufcnt;
6673 dd->lastctxt_piobuf = dd->cspec->lastbuf_for_pio - sbufs;
6674 dd->cspec->lastbuf_for_pio--; /* range is <= , not < */
6675 dd->last_pio = dd->cspec->lastbuf_for_pio;
6687 dd->cspec->updthresh_dflt = updthresh;
6688 dd->cspec->updthresh = updthresh;
6719 last = dd->cspec->lastbuf_for_pio;
6886 n = dd->cspec->sdmabufcnt / dd->num_pports; /* no remainder */
6888 n = dd->cspec->sdmabufcnt; /* failsafe for init */
6891 dd->cspec->sdmabufcnt);
7016 rcd->rcvegrcnt = rcd->dd->cspec->rcvegrcnt;
7077 clear_bit(i, dd->cspec->sendchkenable);
7089 set_bit(i, dd->cspec->sendchkenable);
7095 set_bit(i, dd->cspec->sendibchk);
7096 clear_bit(i, dd->cspec->sendgrhchk);
7101 dd->cspec->updthresh != dd->cspec->updthresh_dflt
7105 < dd->cspec->updthresh_dflt)
7110 dd->cspec->updthresh = dd->cspec->updthresh_dflt;
7112 dd->sendctrl |= (dd->cspec->updthresh &
7123 clear_bit(i, dd->cspec->sendibchk);
7124 set_bit(i, dd->cspec->sendgrhchk);
7128 / rcd->subctxt_cnt) - 1) < dd->cspec->updthresh) {
7129 dd->cspec->updthresh = (rcd->piocnt /
7132 dd->sendctrl |= (dd->cspec->updthresh &
7147 dd->cspec->sendchkenable[i]);
7151 dd->cspec->sendgrhchk[i]);
7153 dd->cspec->sendibchk[i]);
7290 dd->cspec->msix_entries = kcalloc(tabsize,
7293 if (!dd->cspec->msix_entries)
7300 dd->cspec->num_msix_entries = tabsize;
7841 if (ppd->dd->cspec->r1)
7916 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac;
7926 ppd->dd->cspec->r1 ?
7936 if (!ppd->dd->cspec->r1) {
7996 if (!ppd->dd->cspec->r1) {
8096 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac;
8117 ppd->dd->cspec->r1 ?
8232 if (!ppd->dd->cspec->r1)
8433 if (!ppd->dd->cspec->r1)
8436 dd->cspec->recovery_ports_initted++;
8439 if (!both && dd->cspec->recovery_ports_initted == 1) {
8467 if (dd->cspec->recovery_ports_initted != 1)
8480 ppd->dd->cspec->stay_in_freeze = 1;