Lines Matching defs:bits
197 /* ibcctrl bits */
310 /* kr_revision bits */
314 /* kr_control bits */
317 /* kr_intstatus, kr_intclear, kr_intmask bits */
403 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
432 /* kr_ibcddrctrl bits */
460 /* kr_extstatus bits */
466 /* kr_xgxsconfig bits */
487 #define IBA7220_HDRHEAD_PKTINT_SHIFT 32 /* interrupt cnt in upper 32 bits */
490 * the size bits give us 2^N, in KB units. 0 marks as invalid,
496 #define IBA7220_TID_PA_SHIFT 11U /* TID addr in chip stored w/o low bits */
757 * It's possible that sendbuffererror could have bits set; might
1273 * force new interrupt if any hwerr, error or interrupt bits are
1299 u32 bits, ctrl;
1308 "Read of hardware error status failed (all bits set); ignoring\n");
1375 bits = (u32) ((hwerrs >>
1379 "[PCIe Mem Parity Errs %x] ", bits);
1429 * cause a hardware error, and cleared those errors bits as they occur,
1871 * the bits in the mask, since there is some kind of
1911 "error interrupt (%Lx), but no error bits set!\n",
1957 * Clear the interrupt bits we found set, relatively early, so we
2186 * Used from qib_close(). On this chip, TIDs are only 32 bits,
2188 * is declared as u64 * for the pointer math, even though we write 32 bits
2485 /* IBTA 1.2 mode + speed bits are contiguous */
3744 * set output and direction bits selected by mask.
3755 /* some bits being written, lock access to GPIO */
3881 * At least some mask bits are zero, so we need
3884 * if any bits which should be shadowed are different
3901 * At least some mask bits are one, so we need
3902 * to write, but only shadow some bits.
3907 * New shadow val is bits we don't want to touch,
3908 * ORed with bits we do, that are intended for shadow.
3995 * GPIO bits for TWSI data and clock,