Lines Matching refs:dd
298 * @dd: device
306 static inline u32 qib_read_ureg32(const struct qib_devdata *dd,
309 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
312 if (dd->userbase)
314 ((char __iomem *)dd->userbase +
315 dd->ureg_align * ctxt));
318 (dd->uregbase +
319 (char __iomem *)dd->kregbase +
320 dd->ureg_align * ctxt));
325 * @dd: device
332 static inline void qib_write_ureg(const struct qib_devdata *dd,
337 if (dd->userbase)
339 ((char __iomem *) dd->userbase +
340 dd->ureg_align * ctxt);
343 (dd->uregbase +
344 (char __iomem *) dd->kregbase +
345 dd->ureg_align * ctxt);
347 if (dd->kregbase && (dd->flags & QIB_PRESENT))
351 static inline u32 qib_read_kreg32(const struct qib_devdata *dd,
354 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
356 return readl((u32 __iomem *)&dd->kregbase[regno]);
359 static inline u64 qib_read_kreg64(const struct qib_devdata *dd,
362 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
365 return readq(&dd->kregbase[regno]);
368 static inline void qib_write_kreg(const struct qib_devdata *dd,
371 if (dd->kregbase && (dd->flags & QIB_PRESENT))
372 writeq(value, &dd->kregbase[regno]);
377 * @dd: the qlogic_ib device
382 static inline void qib_write_kreg_ctxt(const struct qib_devdata *dd,
386 qib_write_kreg(dd, regno + ctxt, value);
389 static inline void write_6120_creg(const struct qib_devdata *dd,
392 if (dd->cspec->cregbase && (dd->flags & QIB_PRESENT))
393 writeq(value, &dd->cspec->cregbase[regno]);
396 static inline u64 read_6120_creg(const struct qib_devdata *dd, u16 regno)
398 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
400 return readq(&dd->cspec->cregbase[regno]);
403 static inline u32 read_6120_creg32(const struct qib_devdata *dd, u16 regno)
405 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
407 return readl(&dd->cspec->cregbase[regno]);
670 static void qib_6120_txe_recover(struct qib_devdata *dd)
673 qib_devinfo(dd->pcidev,
678 static void qib_6120_set_intr_state(struct qib_devdata *dd, u32 enable)
681 if (dd->flags & QIB_BADINTR)
683 qib_write_kreg(dd, kr_intmask, ~0ULL);
685 qib_write_kreg(dd, kr_intclear, 0ULL);
687 qib_write_kreg(dd, kr_intmask, 0ULL);
705 static void qib_6120_clear_freeze(struct qib_devdata *dd)
708 qib_write_kreg(dd, kr_errmask, 0ULL);
711 qib_6120_set_intr_state(dd, 0);
713 qib_cancel_sends(dd->pport);
716 qib_write_kreg(dd, kr_control, dd->control);
717 qib_read_kreg32(dd, kr_scratch);
720 qib_force_pio_avail_update(dd);
728 qib_write_kreg(dd, kr_hwerrclear, 0ULL);
729 qib_write_kreg(dd, kr_errclear, E_SPKT_ERRS_IGNORE);
730 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
731 qib_6120_set_intr_state(dd, 1);
736 * @dd: the qlogic_ib device
745 static void qib_handle_6120_hwerrors(struct qib_devdata *dd, char *msg,
753 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus);
757 qib_dev_err(dd,
768 qib_write_kreg(dd, kr_hwerrclear,
771 hwerrs &= dd->cspec->hwerrmask;
778 qib_devinfo(dd->pcidev,
783 qib_dev_err(dd,
787 ctrl = qib_read_kreg32(dd, kr_control);
788 if ((ctrl & QLOGIC_IB_C_FREEZEMODE) && !dd->diag_client) {
798 qib_6120_txe_recover(dd);
806 qib_6120_clear_freeze(dd);
819 dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed);
820 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
826 bitsmsg = dd->cspec->bitsmsgbuf;
832 snprintf(bitsmsg, sizeof(dd->cspec->bitsmsgbuf),
839 snprintf(bitsmsg, sizeof(dd->cspec->bitsmsgbuf),
844 dd->cspec->hwerrmask &= ~(hwerrs & _QIB_PLL_FAIL);
845 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
853 dd->cspec->hwerrmask &= ~QLOGIC_IB_HWE_SERDESPLLFAILED;
854 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
864 qib_dev_err(dd, "%s hardware error\n", msg);
868 if (isfatal && !dd->diag_client) {
869 qib_dev_err(dd,
871 dd->serial);
876 if (dd->freezemsg)
877 snprintf(dd->freezemsg, dd->freezelen,
879 qib_disable_after_error(dd);
889 static int qib_decode_6120_err(struct qib_devdata *dd, char *buf, size_t blen,
965 struct qib_devdata *dd = ppd->dd;
971 sbuf[0] = qib_read_kreg64(dd, kr_sendbuffererror);
972 sbuf[1] = qib_read_kreg64(dd, kr_sendbuffererror + 1);
975 qib_disarm_piobufs_set(dd, sbuf,
976 dd->piobcnt2k + dd->piobcnt4k);
979 static int chk_6120_linkrecovery(struct qib_devdata *dd, u64 ibcs)
983 u32 linkrecov = read_6120_creg32(dd, cr_iblinkerrrecov);
985 if (linkrecov != dd->cspec->lastlinkrecov) {
987 dd->cspec->lastlinkrecov = 0;
988 qib_set_linkstate(dd->pport, QIB_IB_LINKDOWN);
992 dd->cspec->lastlinkrecov =
993 read_6120_creg32(dd, cr_iblinkerrrecov);
997 static void handle_6120_errors(struct qib_devdata *dd, u64 errs)
1002 struct qib_pportdata *ppd = dd->pport;
1006 errs &= dd->cspec->errormask;
1007 msg = dd->cspec->emsgbuf;
1011 qib_handle_6120_hwerrors(dd, msg, sizeof(dd->cspec->emsgbuf));
1014 qib_dev_err(dd,
1043 qib_write_kreg(dd, kr_errclear, errs);
1055 qib_decode_6120_err(dd, msg, sizeof(dd->cspec->emsgbuf), errs & ~mask);
1065 u64 ibcs = qib_read_kreg64(dd, kr_ibcstatus);
1069 if (ibstate != IB_PORT_INIT && dd->cspec->lastlinkrecov)
1070 handle = chk_6120_linkrecovery(dd, ibcs);
1086 qib_dev_err(dd,
1088 dd->flags &= ~QIB_INITTED; /* needs re-init */
1090 *dd->devstatusp |= QIB_STATUS_HWERROR;
1091 *dd->pport->statusp &= ~QIB_STATUS_IB_CONF;
1095 qib_dev_porterr(dd, ppd->port, "%s error\n", msg);
1108 qib_handle_urcv(dd, ~0U);
1120 * @dd: the qlogic_ib device
1128 static void qib_6120_init_hwerrors(struct qib_devdata *dd)
1133 extsval = qib_read_kreg64(dd, kr_extstatus);
1136 qib_dev_err(dd, "MemBIST did not complete!\n");
1140 if (dd->minrev < 2) {
1150 dd->cspec->hwerrmask = val;
1152 qib_write_kreg(dd, kr_hwerrclear, ~HWE_MASK(PowerOnBISTFailed));
1153 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
1156 qib_write_kreg(dd, kr_errclear, ~0ULL);
1158 qib_write_kreg(dd, kr_errmask, ~0ULL);
1159 dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask);
1161 qib_write_kreg(dd, kr_intclear, ~0ULL);
1163 qib_write_kreg(dd, kr_rcvbthqp,
1164 dd->qpn_mask << (QIB_6120_RcvBTHQP_BTHQP_Mask_LSB - 1) |
1174 static void qib_set_6120_armlaunch(struct qib_devdata *dd, u32 enable)
1177 qib_write_kreg(dd, kr_errclear,
1179 dd->cspec->errormask |= ERR_MASK(SendPioArmLaunchErr);
1181 dd->cspec->errormask &= ~ERR_MASK(SendPioArmLaunchErr);
1182 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
1194 struct qib_devdata *dd = ppd->dd;
1219 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl | mod_wd);
1221 qib_write_kreg(dd, kr_scratch, 0);
1226 * @dd: the qlogic_ib device
1230 struct qib_devdata *dd = ppd->dd;
1234 dd->control &= ~QLOGIC_IB_C_LINKENABLE;
1235 qib_write_kreg(dd, kr_control, 0ULL);
1237 dd->cspec->ibdeltainprog = 1;
1238 dd->cspec->ibsymsnap = read_6120_creg32(dd, cr_ibsymbolerr);
1239 dd->cspec->iblnkerrsnap = read_6120_creg32(dd, cr_iblinkerrrecov);
1250 dd->cspec->lli_thresh = 0xf;
1251 ibc |= (u64) dd->cspec->lli_thresh << SYM_LSB(IBCCtrl, PhyerrThreshold);
1261 dd->cspec->ibcctrl = ibc; /* without linkcmd or linkinitcmd! */
1264 val = dd->cspec->ibcctrl | (QLOGIC_IB_IBCC_LINKINITCMD_DISABLE <<
1266 qib_write_kreg(dd, kr_ibcctrl, val);
1268 val = qib_read_kreg64(dd, kr_serdes_cfg0);
1269 config1 = qib_read_kreg64(dd, kr_serdes_cfg1);
1283 qib_write_kreg(dd, kr_serdes_cfg0, val);
1285 qib_read_kreg64(dd, kr_scratch);
1303 qib_write_kreg(dd, kr_serdes_cfg0, val);
1305 (void) qib_read_kreg64(dd, kr_scratch);
1315 qib_write_kreg(dd, kr_serdes_cfg0, val);
1317 (void) qib_read_kreg64(dd, kr_scratch);
1319 val = qib_read_kreg64(dd, kr_xgxs_cfg);
1329 qib_write_kreg(dd, kr_xgxs_cfg, val);
1331 val = qib_read_kreg64(dd, kr_serdes_cfg0);
1339 qib_write_kreg(dd, kr_serdes_cfg1, config1);
1342 ppd->guid = dd->base_guid;
1349 hwstat = qib_read_kreg64(dd, kr_hwerrstatus);
1352 qib_write_kreg(dd, kr_hwerrclear, hwstat);
1353 qib_write_kreg(dd, kr_errclear, ERR_MASK(HardwareErr));
1356 dd->control |= QLOGIC_IB_C_LINKENABLE;
1357 dd->control &= ~QLOGIC_IB_C_FREEZEMODE;
1358 qib_write_kreg(dd, kr_control, dd->control);
1370 struct qib_devdata *dd = ppd->dd;
1376 dd->control &= ~QLOGIC_IB_C_LINKENABLE;
1377 qib_write_kreg(dd, kr_control,
1378 dd->control | QLOGIC_IB_C_FREEZEMODE);
1380 if (dd->cspec->ibsymdelta || dd->cspec->iblnkerrdelta ||
1381 dd->cspec->ibdeltainprog) {
1385 diagc = qib_read_kreg64(dd, kr_hwdiagctrl);
1386 qib_write_kreg(dd, kr_hwdiagctrl,
1389 if (dd->cspec->ibsymdelta || dd->cspec->ibdeltainprog) {
1390 val = read_6120_creg32(dd, cr_ibsymbolerr);
1391 if (dd->cspec->ibdeltainprog)
1392 val -= val - dd->cspec->ibsymsnap;
1393 val -= dd->cspec->ibsymdelta;
1394 write_6120_creg(dd, cr_ibsymbolerr, val);
1396 if (dd->cspec->iblnkerrdelta || dd->cspec->ibdeltainprog) {
1397 val = read_6120_creg32(dd, cr_iblinkerrrecov);
1398 if (dd->cspec->ibdeltainprog)
1399 val -= val - dd->cspec->iblnkerrsnap;
1400 val -= dd->cspec->iblnkerrdelta;
1401 write_6120_creg(dd, cr_iblinkerrrecov, val);
1405 qib_write_kreg(dd, kr_hwdiagctrl, diagc);
1408 val = qib_read_kreg64(dd, kr_serdes_cfg0);
1410 qib_write_kreg(dd, kr_serdes_cfg0, val);
1415 * @dd: the qlogic_ib device
1439 struct qib_devdata *dd = ppd->dd;
1445 if (dd->diag_client)
1455 val = qib_read_kreg64(dd, kr_ibcstatus);
1463 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
1464 extctl = dd->cspec->extctrl & ~(SYM_MASK(EXTCtrl, LEDPriPortGreenOn) |
1471 dd->cspec->extctrl = extctl;
1472 qib_write_kreg(dd, kr_extctrl, extctl);
1473 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
1478 * @dd: the qlogic_ib device
1482 static void qib_6120_setup_cleanup(struct qib_devdata *dd)
1484 qib_free_irq(dd);
1485 kfree(dd->cspec->cntrs);
1486 kfree(dd->cspec->portcntrs);
1487 if (dd->cspec->dummy_hdrq) {
1488 dma_free_coherent(&dd->pcidev->dev,
1489 ALIGN(dd->rcvhdrcnt *
1490 dd->rcvhdrentsize *
1492 dd->cspec->dummy_hdrq,
1493 dd->cspec->dummy_hdrq_phys);
1494 dd->cspec->dummy_hdrq = NULL;
1498 static void qib_wantpiobuf_6120_intr(struct qib_devdata *dd, u32 needint)
1502 spin_lock_irqsave(&dd->sendctrl_lock, flags);
1504 dd->sendctrl |= SYM_MASK(SendCtrl, PIOIntBufAvail);
1506 dd->sendctrl &= ~SYM_MASK(SendCtrl, PIOIntBufAvail);
1507 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
1508 qib_write_kreg(dd, kr_scratch, 0ULL);
1509 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
1516 static noinline void unlikely_6120_intr(struct qib_devdata *dd, u64 istat)
1519 qib_dev_err(dd, "interrupt with unknown interrupts %Lx set\n",
1526 estat = qib_read_kreg64(dd, kr_errstatus);
1528 qib_devinfo(dd->pcidev,
1531 handle_6120_errors(dd, estat);
1542 gpiostatus = qib_read_kreg32(dd, kr_gpio_status);
1553 dd->cspec->rxfc_unsupvl_errs++;
1555 dd->cspec->overrun_thresh_errs++;
1557 dd->cspec->lli_errs++;
1567 const u32 mask = qib_read_kreg32(dd, kr_gpio_mask);
1576 dd->cspec->gpio_mask &= ~(gpiostatus & mask);
1577 qib_write_kreg(dd, kr_gpio_mask,
1578 dd->cspec->gpio_mask);
1582 qib_write_kreg(dd, kr_gpio_clear, (u64) to_clear);
1588 struct qib_devdata *dd = data;
1593 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) {
1604 istat = qib_read_kreg32(dd, kr_intstatus);
1611 qib_bad_intrstatus(dd);
1617 this_cpu_inc(*dd->int_counter);
1621 unlikely_6120_intr(dd, istat);
1629 qib_write_kreg(dd, kr_intclear, istat);
1642 for (i = 0; i < dd->first_user_ctxt; i++) {
1645 crcs += qib_kreceive(dd->rcd[i],
1646 &dd->cspec->lli_counter,
1652 u32 cntr = dd->cspec->lli_counter;
1656 if (cntr > dd->cspec->lli_thresh) {
1657 dd->cspec->lli_counter = 0;
1658 dd->cspec->lli_errs++;
1660 dd->cspec->lli_counter += cntr;
1669 qib_handle_urcv(dd, ctxtrbits);
1673 if ((istat & QLOGIC_IB_I_SPIOBUFAVAIL) && (dd->flags & QIB_INITTED))
1674 qib_ib_piobufavail(dd);
1686 static void qib_setup_6120_interrupt(struct qib_devdata *dd)
1696 if (SYM_FIELD(dd->revision, Revision_R,
1699 dd->cspec->gpio_mask |= GPIO_ERRINTR_MASK;
1700 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
1703 ret = pci_request_irq(dd->pcidev, 0, qib_6120intr, NULL, dd,
1706 qib_dev_err(dd,
1708 pci_irq_vector(dd->pcidev, 0), ret);
1713 * @dd: the qlogic_ib device
1717 static void pe_boardname(struct qib_devdata *dd)
1721 boardid = SYM_FIELD(dd->revision, Revision,
1726 dd->boardname = "InfiniPath_QLE7140";
1729 qib_dev_err(dd, "Unknown 6120 board with ID %u\n", boardid);
1730 dd->boardname = "Unknown_InfiniPath_6120";
1734 if (dd->majrev != 4 || !dd->minrev || dd->minrev > 2)
1735 qib_dev_err(dd,
1737 dd->majrev, dd->minrev);
1739 snprintf(dd->boardversion, sizeof(dd->boardversion),
1741 QIB_CHIP_VERS_MAJ, QIB_CHIP_VERS_MIN, dd->boardname,
1742 (unsigned int)SYM_FIELD(dd->revision, Revision_R, Arch),
1743 dd->majrev, dd->minrev,
1744 (unsigned int)SYM_FIELD(dd->revision, Revision_R, SW));
1752 static int qib_6120_setup_reset(struct qib_devdata *dd)
1760 qib_pcie_getcmd(dd, &cmdval, &int_line, &clinesz);
1763 qib_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->unit);
1766 qib_6120_set_intr_state(dd, 0);
1768 dd->cspec->ibdeltainprog = 0;
1769 dd->cspec->ibsymdelta = 0;
1770 dd->cspec->iblnkerrdelta = 0;
1777 dd->flags &= ~(QIB_INITTED | QIB_PRESENT);
1779 dd->z_int_counter = qib_int_counter(dd);
1780 val = dd->control | QLOGIC_IB_C_RESET;
1781 writeq(val, &dd->kregbase[kr_control]);
1792 qib_pcie_reenable(dd, cmdval, int_line, clinesz);
1798 val = readq(&dd->kregbase[kr_revision]);
1799 if (val == dd->revision) {
1800 dd->flags |= QIB_PRESENT; /* it's back */
1801 ret = qib_reinit_intr(dd);
1809 if (qib_pcie_params(dd, dd->lbus_width, NULL))
1810 qib_dev_err(dd,
1813 qib_6120_init_hwerrors(dd);
1815 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
1817 qib_6120_init_hwerrors(dd);
1824 * @dd: the qlogic_ib device
1834 static void qib_6120_put_tid(struct qib_devdata *dd, u64 __iomem *tidptr,
1842 if (!dd->kregbase)
1845 if (pa != dd->tidinvalid) {
1847 qib_dev_err(dd, "Physaddr %lx not 2KB aligned!\n",
1853 qib_dev_err(dd,
1860 pa |= dd->tidtemplate;
1878 tidx = tidptr - dd->egrtidbase;
1880 tidlockp = (type == RCVHQ_RCV_TYPE_EAGER && tidx < dd->rcvhdrcnt)
1881 ? &dd->cspec->kernel_tid_lock : &dd->cspec->user_tid_lock;
1883 qib_write_kreg(dd, kr_scratch, 0xfeeddeaf);
1885 qib_write_kreg(dd, kr_scratch, 0xdeadbeef);
1891 * @dd: the qlogic_ib device
1901 static void qib_6120_put_tid_2(struct qib_devdata *dd, u64 __iomem *tidptr,
1906 if (!dd->kregbase)
1909 if (pa != dd->tidinvalid) {
1911 qib_dev_err(dd, "Physaddr %lx not 2KB aligned!\n",
1917 qib_dev_err(dd,
1924 pa |= dd->tidtemplate;
1934 * @dd: the qlogic_ib device
1942 static void qib_6120_clear_tids(struct qib_devdata *dd,
1950 if (!dd->kregbase || !rcd)
1955 tidinv = dd->tidinvalid;
1957 ((char __iomem *)(dd->kregbase) +
1958 dd->rcvtidbase +
1959 ctxt * dd->rcvtidcnt * sizeof(*tidbase));
1961 for (i = 0; i < dd->rcvtidcnt; i++)
1963 dd->f_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
1967 ((char __iomem *)(dd->kregbase) +
1968 dd->rcvegrbase +
1973 dd->f_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
1979 * @dd: the qlogic_ib device
1983 static void qib_6120_tidtemplate(struct qib_devdata *dd)
1985 u32 egrsize = dd->rcvegrbufsize;
1997 dd->tidtemplate = 1U << 29;
1999 dd->tidtemplate = 2U << 29;
2000 dd->tidinvalid = 0;
2029 qib_6120_get_msgheader(struct qib_devdata *dd, __le32 *rhf_addr)
2035 static void qib_6120_config_ctxts(struct qib_devdata *dd)
2037 dd->ctxtcnt = qib_read_kreg32(dd, kr_portcnt);
2039 dd->first_user_ctxt = qib_n_krcv_queues * dd->num_pports;
2040 if (dd->first_user_ctxt > dd->ctxtcnt)
2041 dd->first_user_ctxt = dd->ctxtcnt;
2042 dd->qpn_mask = dd->first_user_ctxt <= 2 ? 2 : 6;
2044 dd->first_user_ctxt = dd->num_pports;
2045 dd->n_krcv_queues = dd->first_user_ctxt;
2052 qib_write_ureg(rcd->dd, ur_rcvegrindexhead, egrhd, rcd->ctxt);
2053 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
2060 head = qib_read_ureg32(rcd->dd, ur_rcvhdrhead, rcd->ctxt);
2064 tail = qib_read_ureg32(rcd->dd, ur_rcvhdrtail, rcd->ctxt);
2073 static void alloc_dummy_hdrq(struct qib_devdata *dd)
2075 dd->cspec->dummy_hdrq = dma_alloc_coherent(&dd->pcidev->dev,
2076 dd->rcd[0]->rcvhdrq_size,
2077 &dd->cspec->dummy_hdrq_phys,
2079 if (!dd->cspec->dummy_hdrq) {
2080 qib_devinfo(dd->pcidev, "Couldn't allocate dummy hdrq\n");
2082 dd->cspec->dummy_hdrq_phys = 0UL;
2096 struct qib_devdata *dd = ppd->dd;
2100 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
2103 dd->rcvctrl |= (1ULL << QLOGIC_IB_R_TAILUPD_SHIFT);
2105 dd->rcvctrl &= ~(1ULL << QLOGIC_IB_R_TAILUPD_SHIFT);
2107 dd->rcvctrl &= ~(1ULL << IBA6120_R_PKEY_DIS_SHIFT);
2109 dd->rcvctrl |= (1ULL << IBA6120_R_PKEY_DIS_SHIFT);
2111 mask = (1ULL << dd->ctxtcnt) - 1;
2116 dd->rcvctrl |= (mask << SYM_LSB(RcvCtrl, PortEnable));
2117 if (!(dd->flags & QIB_NODMA_RTAIL))
2118 dd->rcvctrl |= 1ULL << QLOGIC_IB_R_TAILUPD_SHIFT;
2120 qib_write_kreg_ctxt(dd, kr_rcvhdrtailaddr, ctxt,
2121 dd->rcd[ctxt]->rcvhdrqtailaddr_phys);
2122 qib_write_kreg_ctxt(dd, kr_rcvhdraddr, ctxt,
2123 dd->rcd[ctxt]->rcvhdrq_phys);
2125 if (ctxt == 0 && !dd->cspec->dummy_hdrq)
2126 alloc_dummy_hdrq(dd);
2129 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, PortEnable));
2131 dd->rcvctrl |= (mask << QLOGIC_IB_R_INTRAVAIL_SHIFT);
2133 dd->rcvctrl &= ~(mask << QLOGIC_IB_R_INTRAVAIL_SHIFT);
2134 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
2135 if ((op & QIB_RCVCTRL_INTRAVAIL_ENB) && dd->rhdrhead_intr_off) {
2137 val = qib_read_ureg32(dd, ur_rcvhdrhead, ctxt) |
2138 dd->rhdrhead_intr_off;
2139 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
2148 val = qib_read_ureg32(dd, ur_rcvegrindextail, ctxt);
2149 qib_write_ureg(dd, ur_rcvegrindexhead, val, ctxt);
2151 val = qib_read_ureg32(dd, ur_rcvhdrtail, ctxt);
2152 dd->rcd[ctxt]->head = val;
2154 if (ctxt < dd->first_user_ctxt)
2155 val |= dd->rhdrhead_intr_off;
2156 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
2169 qib_write_kreg_ctxt(dd, kr_rcvhdrtailaddr, ctxt,
2170 dd->cspec->dummy_hdrq_phys);
2171 qib_write_kreg_ctxt(dd, kr_rcvhdraddr, ctxt,
2172 dd->cspec->dummy_hdrq_phys);
2176 for (i = 0; i < dd->cfgctxts; i++) {
2177 qib_write_kreg_ctxt(dd, kr_rcvhdrtailaddr,
2178 i, dd->cspec->dummy_hdrq_phys);
2179 qib_write_kreg_ctxt(dd, kr_rcvhdraddr,
2180 i, dd->cspec->dummy_hdrq_phys);
2184 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
2197 struct qib_devdata *dd = ppd->dd;
2201 spin_lock_irqsave(&dd->sendctrl_lock, flags);
2205 dd->sendctrl = 0;
2207 dd->sendctrl &= ~SYM_MASK(SendCtrl, PIOEnable);
2209 dd->sendctrl |= SYM_MASK(SendCtrl, PIOEnable);
2211 dd->sendctrl &= ~SYM_MASK(SendCtrl, PIOBufAvailUpd);
2213 dd->sendctrl |= SYM_MASK(SendCtrl, PIOBufAvailUpd);
2218 tmp_dd_sendctrl = dd->sendctrl;
2223 last = dd->piobcnt2k + dd->piobcnt4k;
2228 qib_write_kreg(dd, kr_sendctrl, tmp_dd_sendctrl |
2230 qib_write_kreg(dd, kr_scratch, 0);
2234 tmp_dd_sendctrl = dd->sendctrl;
2245 qib_write_kreg(dd, kr_sendctrl, tmp_dd_sendctrl);
2246 qib_write_kreg(dd, kr_scratch, 0);
2249 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
2250 qib_write_kreg(dd, kr_scratch, 0);
2253 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
2263 v = qib_read_kreg32(dd, kr_scratch);
2264 qib_write_kreg(dd, kr_scratch, v);
2265 v = qib_read_kreg32(dd, kr_scratch);
2266 qib_write_kreg(dd, kr_scratch, v);
2267 qib_read_kreg32(dd, kr_scratch);
2273 * @dd: the qlogic_ib device
2279 struct qib_devdata *dd = ppd->dd;
2320 qib_devinfo(ppd->dd->pcidev,
2328 ret = dd->cspec->lli_errs;
2330 ret = dd->cspec->overrun_thresh_errs;
2335 for (i = 0; i < dd->first_user_ctxt; i++)
2336 ret += read_6120_creg32(dd, cr_portovfl + i);
2338 ret = dd->cspec->pma_sample_status;
2348 ret = read_6120_creg(dd, creg);
2350 ret = read_6120_creg32(dd, creg);
2352 if (dd->cspec->ibdeltainprog)
2353 ret -= ret - dd->cspec->ibsymsnap;
2354 ret -= dd->cspec->ibsymdelta;
2356 if (dd->cspec->ibdeltainprog)
2357 ret -= ret - dd->cspec->iblnkerrsnap;
2358 ret -= dd->cspec->iblnkerrdelta;
2361 ret += dd->cspec->rxfc_unsupvl_errs;
2474 static void init_6120_cntrnames(struct qib_devdata *dd)
2479 for (i = 0, s = (char *)cntr6120names; s && j <= dd->cfgctxts;
2488 dd->cspec->ncntrs = i;
2491 dd->cspec->cntrnamelen = sizeof(cntr6120names) - 1;
2493 dd->cspec->cntrnamelen = 1 + s - cntr6120names;
2494 dd->cspec->cntrs = kmalloc_array(dd->cspec->ncntrs, sizeof(u64),
2499 dd->cspec->nportcntrs = i - 1;
2500 dd->cspec->portcntrnamelen = sizeof(portcntr6120names) - 1;
2501 dd->cspec->portcntrs = kmalloc_array(dd->cspec->nportcntrs,
2506 static u32 qib_read_6120cntrs(struct qib_devdata *dd, loff_t pos, char **namep,
2512 ret = dd->cspec->cntrnamelen;
2518 u64 *cntr = dd->cspec->cntrs;
2521 ret = dd->cspec->ncntrs * sizeof(u64);
2532 for (i = 0; i < dd->cspec->ncntrs; i++)
2533 *cntr++ = read_6120_creg32(dd, cntr6120indices[i]);
2539 static u32 qib_read_6120portcntrs(struct qib_devdata *dd, loff_t pos, u32 port,
2545 ret = dd->cspec->portcntrnamelen;
2551 u64 *cntr = dd->cspec->portcntrs;
2552 struct qib_pportdata *ppd = &dd->pport[port];
2555 ret = dd->cspec->nportcntrs * sizeof(u64);
2562 for (i = 0; i < dd->cspec->nportcntrs; i++) {
2568 *cntr++ = read_6120_creg32(dd,
2576 static void qib_chk_6120_errormask(struct qib_devdata *dd)
2583 if (!dd->cspec->errormask || !(dd->flags & QIB_INITTED))
2586 errormask = qib_read_kreg64(dd, kr_errmask);
2588 if (errormask == dd->cspec->errormask)
2592 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus);
2593 ctrl = qib_read_kreg32(dd, kr_control);
2595 qib_write_kreg(dd, kr_errmask,
2596 dd->cspec->errormask);
2598 if ((hwerrs & dd->cspec->hwerrmask) ||
2600 qib_write_kreg(dd, kr_hwerrclear, 0ULL);
2601 qib_write_kreg(dd, kr_errclear, 0ULL);
2603 qib_write_kreg(dd, kr_intclear, 0ULL);
2604 qib_devinfo(dd->pcidev,
2606 fixed, errormask, (unsigned long)dd->cspec->errormask,
2621 struct qib_devdata *dd = from_timer(dd, t, stats_timer);
2622 struct qib_pportdata *ppd = dd->pport;
2630 if (!(dd->flags & QIB_INITTED) || dd->diag_client)
2641 spin_lock_irqsave(&dd->eep_st_lock, flags);
2642 traffic_wds -= dd->traffic_wds;
2643 dd->traffic_wds += traffic_wds;
2644 spin_unlock_irqrestore(&dd->eep_st_lock, flags);
2646 qib_chk_6120_errormask(dd);
2648 mod_timer(&dd->stats_timer, jiffies + HZ * ACTIVITY_TIMER);
2652 static int qib_6120_nointr_fallback(struct qib_devdata *dd)
2666 struct qib_devdata *dd = ppd->dd;
2668 prev_val = qib_read_kreg64(dd, kr_xgxs_cfg);
2671 qib_write_kreg(dd, kr_control,
2672 dd->control & ~QLOGIC_IB_C_LINKENABLE);
2673 qib_write_kreg(dd, kr_xgxs_cfg, val);
2674 qib_read_kreg32(dd, kr_scratch);
2675 qib_write_kreg(dd, kr_xgxs_cfg, prev_val);
2676 qib_write_kreg(dd, kr_control, dd->control);
2713 ret = SYM_FIELD(ppd->dd->cspec->ibcctrl, IBCCtrl,
2718 ret = SYM_FIELD(ppd->dd->cspec->ibcctrl, IBCCtrl,
2724 ret = (ppd->dd->cspec->ibcctrl &
2749 struct qib_devdata *dd = ppd->dd;
2764 val64 = SYM_FIELD(dd->cspec->ibcctrl, IBCCtrl,
2767 dd->cspec->ibcctrl &=
2769 dd->cspec->ibcctrl |= (u64) val <<
2771 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl);
2772 qib_write_kreg(dd, kr_scratch, 0);
2777 val64 = SYM_FIELD(dd->cspec->ibcctrl, IBCCtrl,
2780 dd->cspec->ibcctrl &=
2782 dd->cspec->ibcctrl |= (u64) val <<
2784 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl);
2785 qib_write_kreg(dd, kr_scratch, 0);
2793 qib_write_kreg(dd, kr_partitionkey, val64);
2799 dd->cspec->ibcctrl &=
2802 dd->cspec->ibcctrl |=
2804 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl);
2805 qib_write_kreg(dd, kr_scratch, 0);
2817 dd->cspec->ibcctrl &= ~SYM_MASK(IBCCtrl, MaxPktLen);
2818 dd->cspec->ibcctrl |= (u64)val <<
2820 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl);
2821 qib_write_kreg(dd, kr_scratch, 0);
2828 if (!dd->cspec->ibdeltainprog) {
2829 dd->cspec->ibdeltainprog = 1;
2830 dd->cspec->ibsymsnap =
2831 read_6120_creg32(dd, cr_ibsymbolerr);
2832 dd->cspec->iblnkerrsnap =
2833 read_6120_creg32(dd, cr_iblinkerrrecov);
2847 qib_dev_err(dd, "bad linkcmd req 0x%x\n", val >> 16);
2869 qib_dev_err(dd, "bad linkinitcmd req 0x%x\n",
2892 ppd->dd->cspec->ibcctrl |= SYM_MASK(IBCCtrl, Loopback);
2893 qib_devinfo(ppd->dd->pcidev, "Enabling IB%u:%u IBC loopback\n",
2894 ppd->dd->unit, ppd->port);
2896 ppd->dd->cspec->ibcctrl &= ~SYM_MASK(IBCCtrl, Loopback);
2897 qib_devinfo(ppd->dd->pcidev,
2899 ppd->dd->unit, ppd->port);
2903 qib_write_kreg(ppd->dd, kr_ibcctrl, ppd->dd->cspec->ibcctrl);
2904 qib_write_kreg(ppd->dd, kr_scratch, 0);
2944 struct qib_chip_specific *cs = ppd->dd->cspec;
3004 if (ppd->dd->cspec->ibdeltainprog) {
3005 ppd->dd->cspec->ibdeltainprog = 0;
3006 ppd->dd->cspec->ibsymdelta +=
3007 read_6120_creg32(ppd->dd, cr_ibsymbolerr) -
3008 ppd->dd->cspec->ibsymsnap;
3009 ppd->dd->cspec->iblnkerrdelta +=
3010 read_6120_creg32(ppd->dd, cr_iblinkerrrecov) -
3011 ppd->dd->cspec->iblnkerrsnap;
3015 ppd->dd->cspec->lli_counter = 0;
3016 if (!ppd->dd->cspec->ibdeltainprog) {
3017 ppd->dd->cspec->ibdeltainprog = 1;
3018 ppd->dd->cspec->ibsymsnap =
3019 read_6120_creg32(ppd->dd, cr_ibsymbolerr);
3020 ppd->dd->cspec->iblnkerrsnap =
3021 read_6120_creg32(ppd->dd, cr_iblinkerrrecov);
3037 static int gpio_6120_mod(struct qib_devdata *dd, u32 out, u32 dir, u32 mask)
3046 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
3047 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe));
3048 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe));
3049 new_out = (dd->cspec->gpio_out & ~mask) | out;
3051 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
3052 qib_write_kreg(dd, kr_gpio_out, new_out);
3053 dd->cspec->gpio_out = new_out;
3054 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
3064 read_val = qib_read_kreg64(dd, kr_extstatus);
3073 static void get_6120_chip_params(struct qib_devdata *dd)
3079 dd->uregbase = qib_read_kreg32(dd, kr_userregbase);
3081 dd->rcvtidcnt = qib_read_kreg32(dd, kr_rcvtidcnt);
3082 dd->rcvtidbase = qib_read_kreg32(dd, kr_rcvtidbase);
3083 dd->rcvegrbase = qib_read_kreg32(dd, kr_rcvegrbase);
3084 dd->palign = qib_read_kreg32(dd, kr_palign);
3085 dd->piobufbase = qib_read_kreg64(dd, kr_sendpiobufbase);
3086 dd->pio2k_bufbase = dd->piobufbase & 0xffffffff;
3088 dd->rcvhdrcnt = qib_read_kreg32(dd, kr_rcvegrcnt);
3090 val = qib_read_kreg64(dd, kr_sendpiosize);
3091 dd->piosize2k = val & ~0U;
3092 dd->piosize4k = val >> 32;
3097 dd->pport->ibmtu = (u32)mtu;
3099 val = qib_read_kreg64(dd, kr_sendpiobufcnt);
3100 dd->piobcnt2k = val & ~0U;
3101 dd->piobcnt4k = val >> 32;
3102 dd->last_pio = dd->piobcnt4k + dd->piobcnt2k - 1;
3104 dd->pio2kbase = (u32 __iomem *)
3105 (((char __iomem *)dd->kregbase) + dd->pio2k_bufbase);
3106 if (dd->piobcnt4k) {
3107 dd->pio4kbase = (u32 __iomem *)
3108 (((char __iomem *) dd->kregbase) +
3109 (dd->piobufbase >> 32));
3115 dd->align4k = ALIGN(dd->piosize4k, dd->palign);
3118 piobufs = dd->piobcnt4k + dd->piobcnt2k;
3120 dd->pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2) /
3129 static void set_6120_baseaddrs(struct qib_devdata *dd)
3133 cregbase = qib_read_kreg32(dd, kr_counterregbase);
3134 dd->cspec->cregbase = (u64 __iomem *)
3135 ((char __iomem *) dd->kregbase + cregbase);
3137 dd->egrtidbase = (u64 __iomem *)
3138 ((char __iomem *) dd->kregbase + dd->rcvegrbase);
3146 static int qib_late_6120_initreg(struct qib_devdata *dd)
3151 qib_write_kreg(dd, kr_rcvhdrentsize, dd->rcvhdrentsize);
3152 qib_write_kreg(dd, kr_rcvhdrsize, dd->rcvhdrsize);
3153 qib_write_kreg(dd, kr_rcvhdrcnt, dd->rcvhdrcnt);
3154 qib_write_kreg(dd, kr_sendpioavailaddr, dd->pioavailregs_phys);
3155 val = qib_read_kreg64(dd, kr_sendpioavailaddr);
3156 if (val != dd->pioavailregs_phys) {
3157 qib_dev_err(dd,
3159 (unsigned long) dd->pioavailregs_phys,
3166 static int init_6120_variables(struct qib_devdata *dd)
3172 ppd = (struct qib_pportdata *)(dd + 1);
3173 dd->pport = ppd;
3174 dd->num_pports = 1;
3176 dd->cspec = (struct qib_chip_specific *)(ppd + dd->num_pports);
3177 dd->cspec->ppd = ppd;
3180 spin_lock_init(&dd->cspec->kernel_tid_lock);
3181 spin_lock_init(&dd->cspec->user_tid_lock);
3182 spin_lock_init(&dd->cspec->rcvmod_lock);
3183 spin_lock_init(&dd->cspec->gpio_lock);
3186 dd->revision = readq(&dd->kregbase[kr_revision]);
3188 if ((dd->revision & 0xffffffffU) == 0xffffffffU) {
3189 qib_dev_err(dd,
3194 dd->flags |= QIB_PRESENT; /* now register routines work */
3196 dd->majrev = (u8) SYM_FIELD(dd->revision, Revision_R,
3198 dd->minrev = (u8) SYM_FIELD(dd->revision, Revision_R,
3201 get_6120_chip_params(dd);
3202 pe_boardname(dd); /* fill in boardname */
3208 dd->gpio_sda_num = _QIB_GPIO_SDA_NUM;
3209 dd->gpio_scl_num = _QIB_GPIO_SCL_NUM;
3210 dd->twsi_eeprom_dev = QIB_TWSI_NO_DEV;
3213 dd->flags |= QIB_PIO_FLUSH_WC;
3215 ret = qib_init_pportdata(ppd, dd, 0, 1);
3228 dd->rcvhdrentsize = QIB_RCVHDR_ENTSIZE;
3229 dd->rcvhdrsize = QIB_DFLT_RCVHDRSIZE;
3230 dd->rhf_offset = 0;
3234 dd->rcvegrbufsize = ret != -1 ? max(ret, 2048) : QIB_DEFAULT_MTU;
3235 dd->rcvegrbufsize_shift = ilog2(dd->rcvegrbufsize);
3237 qib_6120_tidtemplate(dd);
3244 dd->rhdrhead_intr_off = 1ULL << 32;
3247 timer_setup(&dd->stats_timer, qib_get_6120_faststats, 0);
3248 timer_setup(&dd->cspec->pma_timer, pma_6120_timer, 0);
3250 dd->ureg_align = qib_read_kreg32(dd, kr_palign);
3252 dd->piosize2kmax_dwords = dd->piosize2k >> 2;
3253 qib_6120_config_ctxts(dd);
3254 qib_set_ctxtcnt(dd);
3256 ret = init_chip_wc_pat(dd, 0);
3259 set_6120_baseaddrs(dd); /* set chip access pointers now */
3267 ret = qib_create_ctxts(dd);
3268 init_6120_cntrnames(dd);
3271 sbufs = dd->piobcnt4k ? dd->piobcnt4k : 16;
3273 dd->lastctxt_piobuf = dd->piobcnt2k + dd->piobcnt4k - sbufs;
3274 dd->pbufsctxt = dd->lastctxt_piobuf /
3275 (dd->cfgctxts - dd->first_user_ctxt);
3301 u32 lbuf = ppd->dd->piobcnt2k + ppd->dd->piobcnt4k - 1;
3307 sendctrl_6120_mod(ppd->dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
3308 qib_read_kreg64(ppd->dd, kr_scratch); /* extra chip flush */
3309 buf = qib_getsendbuf_range(ppd->dd, bnum, lbuf, lbuf);
3315 ppd->dd->upd_pio_shadow = 1; /* update our idea of what's busy */
3316 qib_read_kreg64(ppd->dd, kr_scratch); /* extra chip flush */
3317 buf = qib_getsendbuf_range(ppd->dd, bnum, lbuf, lbuf);
3326 struct qib_devdata *dd = ppd->dd;
3334 if ((plen + 1) > dd->piosize2kmax_dwords)
3335 first = dd->piobcnt2k;
3339 last = dd->piobcnt2k + dd->piobcnt4k - 1;
3340 buf = qib_getsendbuf_range(dd, pbufnum, first, last);
3382 static void qib_6120_initvl15_bufs(struct qib_devdata *dd)
3388 rcd->rcvegrcnt = rcd->dd->rcvhdrcnt;
3392 static void qib_6120_txchk_change(struct qib_devdata *dd, u32 start,
3397 static void writescratch(struct qib_devdata *dd, u32 val)
3399 (void) qib_write_kreg(dd, kr_scratch, val);
3402 static int qib_6120_tempsense_rd(struct qib_devdata *dd, int regnum)
3408 static int qib_6120_notify_dca(struct qib_devdata *dd, unsigned long event)
3415 static int qib_6120_eeprom_wen(struct qib_devdata *dd, int wen)
3434 struct qib_devdata *dd;
3437 dd = qib_alloc_devdata(pdev, sizeof(struct qib_pportdata) +
3439 if (IS_ERR(dd))
3442 dd->f_bringup_serdes = qib_6120_bringup_serdes;
3443 dd->f_cleanup = qib_6120_setup_cleanup;
3444 dd->f_clear_tids = qib_6120_clear_tids;
3445 dd->f_free_irq = qib_free_irq;
3446 dd->f_get_base_info = qib_6120_get_base_info;
3447 dd->f_get_msgheader = qib_6120_get_msgheader;
3448 dd->f_getsendbuf = qib_6120_getsendbuf;
3449 dd->f_gpio_mod = gpio_6120_mod;
3450 dd->f_eeprom_wen = qib_6120_eeprom_wen;
3451 dd->f_hdrqempty = qib_6120_hdrqempty;
3452 dd->f_ib_updown = qib_6120_ib_updown;
3453 dd->f_init_ctxt = qib_6120_init_ctxt;
3454 dd->f_initvl15_bufs = qib_6120_initvl15_bufs;
3455 dd->f_intr_fallback = qib_6120_nointr_fallback;
3456 dd->f_late_initreg = qib_late_6120_initreg;
3457 dd->f_setpbc_control = qib_6120_setpbc_control;
3458 dd->f_portcntr = qib_portcntr_6120;
3459 dd->f_put_tid = (dd->minrev >= 2) ?
3462 dd->f_quiet_serdes = qib_6120_quiet_serdes;
3463 dd->f_rcvctrl = rcvctrl_6120_mod;
3464 dd->f_read_cntrs = qib_read_6120cntrs;
3465 dd->f_read_portcntrs = qib_read_6120portcntrs;
3466 dd->f_reset = qib_6120_setup_reset;
3467 dd->f_init_sdma_regs = init_sdma_6120_regs;
3468 dd->f_sdma_busy = qib_sdma_6120_busy;
3469 dd->f_sdma_gethead = qib_sdma_6120_gethead;
3470 dd->f_sdma_sendctrl = qib_6120_sdma_sendctrl;
3471 dd->f_sdma_set_desc_cnt = qib_sdma_set_6120_desc_cnt;
3472 dd->f_sdma_update_tail = qib_sdma_update_6120_tail;
3473 dd->f_sendctrl = sendctrl_6120_mod;
3474 dd->f_set_armlaunch = qib_set_6120_armlaunch;
3475 dd->f_set_cntr_sample = qib_set_cntr_6120_sample;
3476 dd->f_iblink_state = qib_6120_iblink_state;
3477 dd->f_ibphys_portstate = qib_6120_phys_portstate;
3478 dd->f_get_ib_cfg = qib_6120_get_ib_cfg;
3479 dd->f_set_ib_cfg = qib_6120_set_ib_cfg;
3480 dd->f_set_ib_loopback = qib_6120_set_loopback;
3481 dd->f_set_intr_state = qib_6120_set_intr_state;
3482 dd->f_setextled = qib_6120_setup_setextled;
3483 dd->f_txchk_change = qib_6120_txchk_change;
3484 dd->f_update_usrhead = qib_update_6120_usrhead;
3485 dd->f_wantpiobuf_intr = qib_wantpiobuf_6120_intr;
3486 dd->f_xgxs_reset = qib_6120_xgxs_reset;
3487 dd->f_writescratch = writescratch;
3488 dd->f_tempsense_rd = qib_6120_tempsense_rd;
3490 dd->f_notify_dca = qib_6120_notify_dca;
3493 * Do remaining pcie setup and save pcie values in dd.
3499 ret = qib_pcie_ddinit(dd, pdev, ent);
3504 ret = init_6120_variables(dd);
3511 if (qib_pcie_params(dd, 8, NULL))
3512 qib_dev_err(dd,
3515 qib_write_kreg(dd, kr_hwdiagctrl, 0);
3517 if (qib_read_kreg64(dd, kr_hwerrstatus) &
3519 qib_write_kreg(dd, kr_hwerrclear,
3523 qib_setup_6120_interrupt(dd);
3525 qib_6120_init_hwerrors(dd);
3530 qib_pcie_ddcleanup(dd);
3532 qib_free_devdata(dd);
3533 dd = ERR_PTR(ret);
3535 return dd;