Lines Matching defs:mdev
358 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
393 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
396 MLX5_CAP_GEN(dev->mdev,
523 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
525 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
535 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
539 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
562 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
564 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
576 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
579 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
1035 mlx5_db_free(dev->mdev, &qp->db);
1037 mlx5_frag_buf_free(dev->mdev, &qp->buf);
1059 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
1072 err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size,
1073 &qp->buf, dev->mdev->priv.numa_node);
1118 err = mlx5_db_alloc(dev->mdev, &qp->db);
1149 mlx5_db_free(dev->mdev, &qp->db);
1155 mlx5_frag_buf_free(dev->mdev, &qp->buf);
1183 return mlx5_core_create_tis(dev->mdev, in, &sq->tisn);
1189 mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid);
1233 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1240 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1241 MLX5_CAP_ETH(dev->mdev, swp))
1368 mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid);
1408 err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out);
1480 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) ||
1481 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner_v2)) {
1549 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1726 err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out);
1733 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1743 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) ||
1744 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner_v2)) {
1791 MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe))
1817 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
1818 u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic);
1826 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
1828 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
1850 struct mlx5_core_dev *mdev = dev->mdev;
1888 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
1906 if (MLX5_CAP_GEN(mdev, ece_support))
1928 struct mlx5_core_dev *mdev = dev->mdev;
1967 if (ucmd->sq_wqe_count > (1 << MLX5_CAP_GEN(mdev, log_max_qp_sz)))
1978 if (MLX5_CAP_GEN(mdev, ece_support))
2056 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
2082 if (MLX5_CAP_GEN(mdev, ece_support))
2118 struct mlx5_core_dev *mdev = dev->mdev;
2199 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
2411 if (mlx5_lag_is_active(dev->mdev) && !MLX5_CAP_GEN(dev->mdev, lag_dct))
2425 if (MLX5_CAP_GEN(dev->mdev, ece_support))
2443 if (attr->qp_type == IB_QPT_DRIVER && !MLX5_CAP_GEN(dev->mdev, dct))
2449 if (!MLX5_CAP_GEN(dev->mdev, xrc))
2549 struct mlx5_core_dev *mdev = dev->mdev;
2580 MLX5_CAP_GEN(mdev, sctr_data_cqe), qp);
2582 MLX5_CAP_GEN(mdev, sctr_data_cqe), qp);
2585 cond = MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan) ||
2586 MLX5_CAP_ETH(mdev, tunnel_stateless_gre) ||
2587 MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx);
2601 MLX5_CAP_GEN(mdev, qp_packet_based), qp);
2648 struct mlx5_core_dev *mdev = dev->mdev;
2659 mlx5_get_flow_namespace(dev->mdev,
2664 MLX5_CAP_GEN(mdev, sho), qp);
2667 MLX5_CAP_GEN(mdev, block_lb_mc), qp);
2669 MLX5_CAP_GEN(mdev, cd), qp);
2671 MLX5_CAP_GEN(mdev, cd), qp);
2673 MLX5_CAP_GEN(mdev, cd), qp);
2678 MLX5_CAP_GEN(mdev, ipoib_basic_offloads),
2680 cond = MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_IB;
2686 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) &&
2687 MLX5_CAP_ETH(mdev, scatter_fcs);
2691 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) &&
2692 MLX5_CAP_ETH(mdev, vlan_cap);
2699 MLX5_CAP_GEN(mdev, end_pad), qp);
3124 stat_rate_support = MLX5_CAP_GEN(dev->mdev, stat_rate_support);
3215 dev->mdev->port_caps[port - 1].gid_table_len) {
3218 dev->mdev->port_caps[port - 1].gid_table_len);
3272 return modify_raw_packet_eth_prio(dev->mdev,
3470 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
3480 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in);
3623 err = modify_raw_packet_tx_affinity(dev->mdev, sq,
3635 err = modify_raw_packet_qp_sq(dev->mdev, sq, sq_state,
3659 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3703 mlx5_lag_get_slave_port(dev->mdev, attr->xmit_slave);
3718 struct mlx5_core_dev *mdev)
3738 return mlx5_core_modify_rq(mdev, rq->base.mqp.qpn, in);
3757 return __mlx5_ib_qp_set_raw_qp_counter(mqp, set_id, dev->mdev);
3768 return mlx5_cmd_exec_in(dev->mdev, rts2rts_qp, in);
3863 MLX5_CAP_GEN(dev->mdev, init2_lag_tx_port_affinity))
3883 MLX5_CAP_GEN(dev->mdev, log_max_msg));
4022 MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) {
4033 MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) {
4050 MLX5_CAP_GEN(dev->mdev, ece_support) ?
4177 if (MLX5_CAP_GEN(dev->mdev, ece_support) && ucmd->ece_options)
4214 if (mlx5_lag_is_active(dev->mdev))
4255 if (MLX5_CAP_GEN(dev->mdev, ece_support))
4295 log_max_ra_res = 1 << MLX5_CAP_GEN(dev->mdev,
4297 log_max_ra_req = 1 << MLX5_CAP_GEN(dev->mdev,
4300 log_max_ra_res = 1 << MLX5_CAP_GEN(dev->mdev,
4302 log_max_ra_req = 1 << MLX5_CAP_GEN(dev->mdev,
4409 dev->mdev->port_caps[port - 1].pkey_table_len) {
4500 err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state);
4523 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4810 if (!MLX5_CAP_GEN(dev->mdev, xrc))
4813 return mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0);
4821 return mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0);
4899 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
4931 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
4933 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
4942 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
4982 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
5004 if (!MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) &&
5044 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
5064 MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) ?
5192 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
5195 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
5220 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
5238 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
5247 return mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
5298 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
5299 MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5322 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
5332 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in);
5360 struct mlx5_core_dev *mdev = dev->mdev;
5368 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5420 struct mlx5_core_dev *mdev = dev->mdev;
5423 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5449 struct mlx5_core_dev *mdev = dev->mdev;
5452 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5486 if (!MLX5_CAP_GEN(dev->mdev, rts2rts_qp_counters_set_id)) {