Lines Matching defs:mdev
111 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
134 struct mlx5_eswitch *esw = dev->mdev->priv.eswitch;
164 struct mlx5_core_dev *mdev;
168 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
169 if (!mdev)
178 if (ndev->dev.parent == mdev->device)
194 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
246 struct mlx5_core_dev *mdev;
248 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
249 if (!mdev)
252 ndev = mlx5_lag_get_roce_netdev(mdev);
275 struct mlx5_core_dev *mdev = NULL;
279 if (!mlx5_core_mp_enabled(ibdev->mdev) ||
283 return ibdev->mdev;
293 mdev = mpi->mdev;
302 return mdev;
312 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
470 struct mlx5_core_dev *mdev;
480 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
481 if (!mdev) {
486 mdev = dev->mdev;
496 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
499 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
515 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
518 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
523 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
595 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
621 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
626 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
627 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
654 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
656 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
674 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
683 struct mlx5_core_dev *mdev = dev->mdev;
693 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
697 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
715 struct mlx5_core_dev *mdev = dev->mdev;
723 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
743 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
761 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
765 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
791 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
802 struct mlx5_core_dev *mdev = dev->mdev;
807 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
808 bool raw_support = !mlx5_core_mp_enabled(mdev);
836 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
837 (fw_rev_min(dev->mdev) << 16) |
838 fw_rev_sub(dev->mdev);
844 if (MLX5_CAP_GEN(mdev, pkv))
846 if (MLX5_CAP_GEN(mdev, qkv))
848 if (MLX5_CAP_GEN(mdev, apm))
850 if (MLX5_CAP_GEN(mdev, xrc))
852 if (MLX5_CAP_GEN(mdev, imaicl)) {
855 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
860 if (!MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled))
862 if (MLX5_CAP_GEN(mdev, sho)) {
871 if (MLX5_CAP_GEN(mdev, block_lb_mc))
874 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
875 if (MLX5_CAP_ETH(mdev, csum_cap)) {
881 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
886 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
908 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
921 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
926 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
927 MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
931 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
932 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
935 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
936 MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
943 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
945 MLX5_CAP_DEV_MEM(mdev, max_memic_size);
948 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
951 if (MLX5_CAP_GEN(mdev, end_pad))
954 props->vendor_part_id = mdev->pdev->device;
955 props->hw_ver = mdev->pdev->revision;
959 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
960 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
961 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
963 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
970 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
971 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
972 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
973 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
974 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
975 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
976 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
977 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
978 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
982 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
986 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance);
989 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
990 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
994 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
1020 if (MLX5_CAP_GEN(mdev, cd))
1023 if (mlx5_core_is_vf(mdev))
1029 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
1031 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
1034 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
1037 if (MLX5_CAP_GEN(mdev, tag_matching)) {
1039 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
1041 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1045 if (MLX5_CAP_GEN(mdev, tag_matching) &&
1046 MLX5_CAP_GEN(mdev, rndv_offload_rc)) {
1051 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
1061 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
1063 MLX5_CAP_GEN(dev->mdev,
1070 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
1078 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
1079 MLX5_CAP_GEN(mdev, qos)) {
1081 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
1083 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
1086 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
1087 MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
1096 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
1100 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1111 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1115 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1117 if (MLX5_CAP_GEN(mdev, qp_packet_based))
1126 if (MLX5_CAP_ETH(mdev, swp)) {
1130 if (MLX5_CAP_ETH(mdev, swp_csum))
1134 if (MLX5_CAP_ETH(mdev, swp_lso))
1147 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1152 if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range))
1169 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1172 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1175 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1178 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre))
1181 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp))
1285 struct mlx5_core_dev *mdev = dev->mdev;
1301 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
1312 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1313 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1314 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1323 err = mlx5_query_ib_port_oper(mdev, &ib_link_width_oper,
1330 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
1334 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
1338 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1374 struct mlx5_core_dev *mdev;
1377 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1378 if (!mdev) {
1382 mdev = dev->mdev;
1386 count = mlx5_core_reserved_gids_count(mdev);
1416 struct mlx5_core_dev *mdev = dev->mdev;
1423 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1435 struct mlx5_core_dev *mdev;
1440 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1441 if (!mdev) {
1446 mdev = dev->mdev;
1450 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1492 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1506 struct mlx5_core_dev *mdev;
1510 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1511 if (!mdev)
1514 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
1527 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1554 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1569 err = mlx5_set_port_caps(dev->mdev, port, tmp);
1621 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1637 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1651 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1667 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1683 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1704 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1717 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1720 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid);
1724 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1725 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1726 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1735 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1738 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid);
1740 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1741 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1742 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1757 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1758 err = mlx5_cmd_dump_fill_mkey(dev->mdev,
1766 resp->qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1768 resp->bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev,
1771 resp->max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1772 resp->max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1773 resp->max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1774 resp->max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1775 resp->max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1777 resp->log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1779 resp->num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1780 MLX5_CAP_GEN(dev->mdev,
1783 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
1785 if (mlx5_get_flow_namespace(dev->mdev,
1788 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
1791 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1793 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
1806 mlx5_query_min_inline(dev->mdev, &resp->eth_min_inline);
1810 if (dev->mdev->clock_info)
1827 if (MLX5_CAP_GEN(dev->mdev, ece_support))
1927 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1945 u8 port = mlx5_core_native_port_num(dev->mdev) - 1;
2018 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
2020 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
2028 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
2031 return (dev->mdev->bar_addr + (uar_idx / fw_uars_per_page) * PAGE_SIZE);
2091 if (!dev->mdev->clock_info)
2095 virt_to_page(dev->mdev->clock_info));
2120 mlx5_cmd_free_uar(dev->mdev, mentry->page_idx);
2198 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2227 mlx5_cmd_free_uar(dev->mdev, idx);
2332 pfn = (dev->mdev->iseg_base +
2354 if (!MLX5_CAP_DEV_MEM(dev->mdev, memic))
2363 if (!(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) ||
2364 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, sw_owner) ||
2365 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner_v2) ||
2366 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, sw_owner_v2)))
2428 struct mlx5_core_dev *dev = to_mdev(ctx->device)->mdev;
2518 struct mlx5_core_dev *dev = to_mdev(ibdm->device)->mdev;
2564 err = mlx5_cmd_exec_inout(to_mdev(ibdev)->mdev, alloc_pd, in, out);
2573 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid);
2583 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2586 return mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid);
2604 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
2620 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
2636 dev->mdev->rev_id = dev->mdev->pdev->revision;
2647 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
2657 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
2667 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
2677 return sprintf(buf, "%x\n", dev->mdev->rev_id);
2688 dev->mdev->board_id);
2948 for (port = 1; port <= ARRAY_SIZE(dev->mdev->port_caps); port++) {
2949 dev->mdev->port_caps[port - 1].has_smi = false;
2950 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
2952 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
2953 err = mlx5_query_hca_vport_context(dev->mdev, 0,
2961 dev->mdev->port_caps[port - 1].has_smi =
2964 dev->mdev->port_caps[port - 1].has_smi = true;
3006 dev->mdev->port_caps[port - 1].pkey_table_len =
3008 dev->mdev->port_caps[port - 1].gid_table_len =
3053 if (!MLX5_CAP_GEN(dev->mdev, xrc))
3083 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn0, 0);
3087 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn1, 0);
3150 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0);
3152 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0);
3173 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0);
3174 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0);
3190 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
3191 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
3192 bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
3233 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
3271 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
3272 fw_rev_sub(dev->mdev));
3277 struct mlx5_core_dev *mdev = dev->mdev;
3278 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
3283 if (!ns || !mlx5_lag_is_roce(mdev))
3286 err = mlx5_cmd_create_vport_lag(mdev);
3301 mlx5_cmd_destroy_vport_lag(mdev);
3307 struct mlx5_core_dev *mdev = dev->mdev;
3315 mlx5_cmd_destroy_vport_lag(mdev);
3345 err = mlx5_nic_vport_enable_roce(dev->mdev);
3356 mlx5_nic_vport_disable_roce(dev->mdev);
3364 mlx5_nic_vport_disable_roce(dev->mdev);
3374 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params);
3419 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
3439 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events);
3461 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
3477 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
3495 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
3499 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
3511 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events);
3524 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3531 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
3534 err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
3539 err = mlx5_nic_vport_enable_roce(dev->mdev);
3552 mlx5_nic_vport_disable_roce(dev->mdev);
3557 mpi->mdev = dev->mdev;
3568 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
3573 dev_dbg(mpi->mdev->device,
3594 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3599 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
3622 mlx5_nic_vport_disable_roce(dev->mdev);
3762 return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
3780 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
3798 mlx5_cmd_free_uar(dev->mdev, uar_index);
3947 struct mlx5_core_dev *mdev = dev->mdev;
3969 if (!mlx5_core_mp_enabled(mdev)) {
3976 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
3987 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_count(mdev);
3988 dev->ib_dev.dev.parent = mdev->device;
4003 dev->dm.dev = mdev;
4013 struct mlx5_ib_dev *mdev = to_mdev(dev);
4016 ret = mlx5_ib_test_wc(mdev);
4017 mlx5_ib_dbg(mdev, "Write-Combining %s",
4018 mdev->wc_support ? "supported" : "not supported");
4123 struct mlx5_core_dev *mdev = dev->mdev;
4129 log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev,
4131 log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev,
4133 var_table->hw_start_addr = dev->mdev->bar_addr +
4134 MLX5_CAP64_DEV_VDPA_EMULATION(mdev,
4153 struct mlx5_core_dev *mdev = dev->mdev;
4188 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
4193 if (mlx5_core_is_pf(mdev))
4196 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
4198 if (MLX5_CAP_GEN(mdev, imaicl)) {
4205 if (MLX5_CAP_GEN(mdev, xrc)) {
4212 if (MLX5_CAP_DEV_MEM(mdev, memic) ||
4213 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
4226 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
4227 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
4228 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
4231 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
4279 struct mlx5_core_dev *mdev = dev->mdev;
4285 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4291 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4295 if (err || dev->is_rep || !mlx5_is_roce_enabled(mdev))
4316 struct mlx5_core_dev *mdev = dev->mdev;
4321 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4328 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4336 mlx5_core_native_port_num(dev->mdev) - 1);
4343 mlx5_core_native_port_num(dev->mdev) - 1);
4348 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
4349 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
4354 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
4361 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
4365 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
4367 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4374 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4375 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4383 if (!mlx5_lag_is_roce(dev->mdev))
4387 return ib_register_device(&dev->ib_dev, name, &dev->mdev->pdev->dev);
4544 root = debugfs_create_dir("delay_drop", dev->mdev->priv.dbg_root);
4572 mlx5_notifier_register(dev->mdev, &dev->mdev_events);
4578 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events);
4747 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev)
4758 mpi->mdev = mdev;
4760 err = mlx5_query_nic_vport_system_image_guid(mdev,
4781 dev_dbg(mdev->device,
4789 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
4797 if (MLX5_ESWITCH_MANAGER(mdev) &&
4798 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == MLX5_ESWITCH_OFFLOADS) {
4799 if (!mlx5_core_mp_enabled(mdev))
4800 mlx5_ib_register_vport_reps(mdev);
4801 return mdev;
4804 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4807 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET)
4808 return mlx5_ib_add_slave_port(mdev);
4810 num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
4811 MLX5_CAP_GEN(mdev, num_vhca_ports));
4822 dev->mdev = mdev;
4825 if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_is_roce_enabled(mdev))
4833 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
4838 if (MLX5_ESWITCH_MANAGER(mdev) && context == mdev) {
4839 mlx5_ib_unregister_vport_reps(mdev);
4843 if (mlx5_core_is_mp_slave(mdev)) {