Lines Matching defs:attr_mask
166 u32 var, u32 *attr_mask)
170 *attr_mask |= MLX5_IB_RP_CLAMP_TGT_RATE_ATTR;
175 *attr_mask |= MLX5_IB_RP_CLAMP_TGT_RATE_ATI_ATTR;
180 *attr_mask |= MLX5_IB_RP_TIME_RESET_ATTR;
185 *attr_mask |= MLX5_IB_RP_BYTE_RESET_ATTR;
190 *attr_mask |= MLX5_IB_RP_THRESHOLD_ATTR;
195 *attr_mask |= MLX5_IB_RP_AI_RATE_ATTR;
200 *attr_mask |= MLX5_IB_RP_MAX_RATE_ATTR;
205 *attr_mask |= MLX5_IB_RP_HAI_RATE_ATTR;
210 *attr_mask |= MLX5_IB_RP_MIN_DEC_FAC_ATTR;
215 *attr_mask |= MLX5_IB_RP_MIN_RATE_ATTR;
220 *attr_mask |= MLX5_IB_RP_RATE_TO_SET_ON_FIRST_CNP_ATTR;
225 *attr_mask |= MLX5_IB_RP_DCE_TCP_G_ATTR;
230 *attr_mask |= MLX5_IB_RP_DCE_TCP_RTT_ATTR;
235 *attr_mask |= MLX5_IB_RP_RATE_REDUCE_MONITOR_PERIOD_ATTR;
240 *attr_mask |= MLX5_IB_RP_INITIAL_ALPHA_VALUE_ATTR;
245 *attr_mask |= MLX5_IB_RP_GD_ATTR;
250 *attr_mask |= MLX5_IB_NP_MIN_TIME_BETWEEN_CNPS_ATTR;
255 *attr_mask |= MLX5_IB_NP_CNP_DSCP_ATTR;
259 *attr_mask |= MLX5_IB_NP_CNP_PRIO_MODE_ATTR;
263 *attr_mask |= MLX5_IB_NP_CNP_PRIO_MODE_ATTR;
315 u32 attr_mask = 0;
336 mlx5_ib_set_cc_param_mask_val(field, offset, var, &attr_mask);
340 attr_mask);