Lines Matching refs:info
128 * @info: ptr to i40iw_hmc_obj_info struct
131 * parses fpm commit info and copy base value
136 struct i40iw_hmc_obj_info *info,
150 info[i].base = 0;
151 info[i].cnt = 0;
155 info[i].base = RS_64_1(temp, 32) * 512;
156 if (info[i].base > base) {
157 base = info[i].base;
161 info[i].cnt = 1;
165 info[i].cnt = (u32)RS_64(temp, I40IW_QUERY_FPM_MAX_QPS);
167 info[i].cnt = (u32)RS_64(temp, I40IW_QUERY_FPM_MAX_CQS);
169 info[i].cnt = (u32)(temp);
171 size = info[k].cnt * info[k].size + info[k].base;
184 * @info: ptr to i40iw_hmc_obj_info struct
185 * @rsrc_idx: resource index into info
208 * @info: ptr to i40iw_hmc_obj_info struct
451 * @info: IWARP control queue pair init info pointer
456 struct i40iw_cqp_init_info *info)
460 if ((info->sq_size > I40IW_CQP_SW_SQSIZE_2048) ||
461 (info->sq_size < I40IW_CQP_SW_SQSIZE_4) ||
462 ((info->sq_size & (info->sq_size - 1))))
465 hw_sq_size = i40iw_get_encoded_wqe_size(info->sq_size, true);
467 cqp->sq_size = info->sq_size;
469 cqp->sq_base = info->sq;
470 cqp->host_ctx = info->host_ctx;
471 cqp->sq_pa = info->sq_pa;
472 cqp->host_ctx_pa = info->host_ctx_pa;
473 cqp->dev = info->dev;
474 cqp->struct_ver = info->struct_ver;
475 cqp->scratch_array = info->scratch_array;
477 cqp->en_datacenter_tcp = info->en_datacenter_tcp;
478 cqp->enabled_vf_count = info->enabled_vf_count;
479 cqp->hmc_profile = info->hmc_profile;
480 info->dev->cqp = cqp;
717 * @info: completion q entry to return
721 struct i40iw_ccq_cqe_info *info)
742 info->error = (bool)RS_64(temp, I40IW_CQ_ERROR);
743 info->min_err_code = (u16)RS_64(temp, I40IW_CQ_MINERR);
744 if (info->error) {
745 info->maj_err_code = (u16)RS_64(temp, I40IW_CQ_MAJERR);
746 info->min_err_code = (u16)RS_64(temp, I40IW_CQ_MINERR);
749 info->scratch = cqp->scratch_array[wqe_idx];
752 info->op_ret_val = (u32)RS_64(temp1, I40IW_CCQ_OPRETVAL);
754 info->op_code = (u8)RS_64(temp1, I40IW_CQPSQ_OPCODE);
755 info->cqp = cqp;
778 * @info: completion q entry to return
785 struct i40iw_ccq_cqe_info info;
790 memset(&info, 0, sizeof(info));
796 if (i40iw_sc_ccq_get_cqe_info(ccq, &info)) {
801 if (info.error) {
806 if (op_code != info.op_code) {
809 __func__, op_code, info.op_code);
812 if (op_code == info.op_code)
817 memcpy(compl_info, &info, sizeof(*compl_info));
825 * @info: push page info
831 struct i40iw_cqp_manage_push_page_info *info,
838 if (info->push_idx >= I40IW_MAX_PUSH_PAGE_COUNT)
845 set_64bit_val(wqe, 16, info->qs_handle);
847 header = LS_64(info->push_idx, I40IW_CQPSQ_MPP_PPIDX) |
850 LS_64(info->free_page, I40IW_CQPSQ_MPP_FREE_PAGE);
1179 * @info: arp entry information
1185 struct i40iw_add_arp_cache_entry_info *info,
1195 set_64bit_val(wqe, 8, info->reach_max);
1197 temp = info->mac_addr[5] |
1198 LS_64_1(info->mac_addr[4], 8) |
1199 LS_64_1(info->mac_addr[3], 16) |
1200 LS_64_1(info->mac_addr[2], 24) |
1201 LS_64_1(info->mac_addr[1], 32) |
1202 LS_64_1(info->mac_addr[0], 40);
1206 header = info->arp_index |
1208 LS_64((info->permanent ? 1 : 0), I40IW_CQPSQ_MAT_PERMANENT) |
1293 * @info: info for apbvt entry to add or delete
1299 struct i40iw_apbvt_info *info,
1310 set_64bit_val(wqe, 16, info->port);
1313 LS_64(info->add, I40IW_CQPSQ_MAPT_ADDPORT) |
1329 * @info: info for quad hash to manage
1337 * I40IW_QHASH_TYPE_TCP_ESTABLISHED and quad is passed in info.
1344 struct i40iw_qhash_table_info *info,
1352 struct i40iw_sc_vsi *vsi = info->vsi;
1358 temp = info->mac_addr[5] |
1359 LS_64_1(info->mac_addr[4], 8) |
1360 LS_64_1(info->mac_addr[3], 16) |
1361 LS_64_1(info->mac_addr[2], 24) |
1362 LS_64_1(info->mac_addr[1], 32) |
1363 LS_64_1(info->mac_addr[0], 40);
1367 qw1 = LS_64(info->qp_num, I40IW_CQPSQ_QHASH_QPN) |
1368 LS_64(info->dest_port, I40IW_CQPSQ_QHASH_DEST_PORT);
1369 if (info->ipv4_valid) {
1372 LS_64(info->dest_ip[0], I40IW_CQPSQ_QHASH_ADDR3));
1376 LS_64(info->dest_ip[0], I40IW_CQPSQ_QHASH_ADDR0) |
1377 LS_64(info->dest_ip[1], I40IW_CQPSQ_QHASH_ADDR1));
1381 LS_64(info->dest_ip[2], I40IW_CQPSQ_QHASH_ADDR2) |
1382 LS_64(info->dest_ip[3], I40IW_CQPSQ_QHASH_ADDR3));
1384 qw2 = LS_64(vsi->qos[info->user_pri].qs_handle, I40IW_CQPSQ_QHASH_QS_HANDLE);
1385 if (info->vlan_valid)
1386 qw2 |= LS_64(info->vlan_id, I40IW_CQPSQ_QHASH_VLANID);
1388 if (info->entry_type == I40IW_QHASH_TYPE_TCP_ESTABLISHED) {
1389 qw1 |= LS_64(info->src_port, I40IW_CQPSQ_QHASH_SRC_PORT);
1390 if (!info->ipv4_valid) {
1393 LS_64(info->src_ip[0], I40IW_CQPSQ_QHASH_ADDR0) |
1394 LS_64(info->src_ip[1], I40IW_CQPSQ_QHASH_ADDR1));
1397 LS_64(info->src_ip[2], I40IW_CQPSQ_QHASH_ADDR2) |
1398 LS_64(info->src_ip[3], I40IW_CQPSQ_QHASH_ADDR3));
1402 LS_64(info->src_ip[0], I40IW_CQPSQ_QHASH_ADDR3));
1409 LS_64(info->manage, I40IW_CQPSQ_QHASH_MANAGE) |
1410 LS_64(info->ipv4_valid, I40IW_CQPSQ_QHASH_IPV4VALID) |
1411 LS_64(info->vlan_valid, I40IW_CQPSQ_QHASH_VLANVALID) |
1412 LS_64(info->entry_type, I40IW_CQPSQ_QHASH_ENTRYTYPE);
1455 * @info:mac addr info
1461 struct i40iw_local_mac_ipaddr_entry_info *info,
1471 temp = info->mac_addr[5] |
1472 LS_64_1(info->mac_addr[4], 8) |
1473 LS_64_1(info->mac_addr[3], 16) |
1474 LS_64_1(info->mac_addr[2], 24) |
1475 LS_64_1(info->mac_addr[1], 32) |
1476 LS_64_1(info->mac_addr[0], 40);
1480 header = LS_64(info->entry_idx, I40IW_CQPSQ_MLIPA_IPTABLEIDX) |
1561 * @info: ceq initialization info
1564 struct i40iw_ceq_init_info *info)
1568 if ((info->elem_cnt < I40IW_MIN_CEQ_ENTRIES) ||
1569 (info->elem_cnt > I40IW_MAX_CEQ_ENTRIES))
1572 if (info->ceq_id >= I40IW_MAX_CEQID)
1575 pble_obj_cnt = info->dev->hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt;
1577 if (info->virtual_map && (info->first_pm_pbl_idx >= pble_obj_cnt))
1581 ceq->ceqe_base = (struct i40iw_ceqe *)info->ceqe_base;
1582 ceq->ceq_id = info->ceq_id;
1583 ceq->dev = info->dev;
1584 ceq->elem_cnt = info->elem_cnt;
1585 ceq->ceq_elem_pa = info->ceqe_pa;
1586 ceq->virtual_map = info->virtual_map;
1588 ceq->pbl_chunk_size = (ceq->virtual_map ? info->pbl_chunk_size : 0);
1589 ceq->first_pm_pbl_idx = (ceq->virtual_map ? info->first_pm_pbl_idx : 0);
1590 ceq->pbl_list = (ceq->virtual_map ? info->pbl_list : NULL);
1592 ceq->tph_en = info->tph_en;
1593 ceq->tph_val = info->tph_val;
1596 ceq->dev->ceq[info->ceq_id] = ceq;
1751 * @info: aeq initialization info
1754 struct i40iw_aeq_init_info *info)
1758 if ((info->elem_cnt < I40IW_MIN_AEQ_ENTRIES) ||
1759 (info->elem_cnt > I40IW_MAX_AEQ_ENTRIES))
1761 pble_obj_cnt = info->dev->hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt;
1763 if (info->virtual_map && (info->first_pm_pbl_idx >= pble_obj_cnt))
1768 aeq->aeqe_base = (struct i40iw_sc_aeqe *)info->aeqe_base;
1769 aeq->dev = info->dev;
1770 aeq->elem_cnt = info->elem_cnt;
1772 aeq->aeq_elem_pa = info->aeq_elem_pa;
1774 info->dev->aeq = aeq;
1776 aeq->virtual_map = info->virtual_map;
1777 aeq->pbl_list = (aeq->virtual_map ? info->pbl_list : NULL);
1778 aeq->pbl_chunk_size = (aeq->virtual_map ? info->pbl_chunk_size : 0);
1779 aeq->first_pm_pbl_idx = (aeq->virtual_map ? info->first_pm_pbl_idx : 0);
1780 info->dev->aeq = aeq;
1857 * @info: aeqe info to be returned
1860 struct i40iw_aeqe_info *info)
1880 info->qp_cq_id = (u32)RS_64(temp, I40IW_AEQE_QPCQID);
1881 info->ae_id = (u16)RS_64(temp, I40IW_AEQE_AECODE);
1882 info->tcp_state = (u8)RS_64(temp, I40IW_AEQE_TCPSTATE);
1883 info->iwarp_state = (u8)RS_64(temp, I40IW_AEQE_IWSTATE);
1884 info->q2_data_written = (u8)RS_64(temp, I40IW_AEQE_Q2DATA);
1885 info->aeqe_overflow = (bool)RS_64(temp, I40IW_AEQE_OVERFLOW);
1887 switch (info->ae_id) {
1922 info->qp = true;
1923 info->compl_ctx = compl_ctx;
1927 info->cq = true;
1928 info->compl_ctx = LS_64_1(compl_ctx, 1);
1936 info->qp = true;
1937 info->wqe_idx = wqe_idx;
1938 info->compl_ctx = compl_ctx;
1944 info->cq = true;
1945 info->compl_ctx = LS_64_1(compl_ctx, 1);
1949 info->qp = true;
1950 info->sq = true;
1951 info->wqe_idx = wqe_idx;
1952 info->compl_ctx = compl_ctx;
1956 info->qp = true;
1957 info->compl_ctx = compl_ctx;
1958 info->in_rdrsp_wr = true;
1962 info->qp = true;
1963 info->compl_ctx = compl_ctx;
1964 info->out_rdrsp = true;
2020 * @info: info for control cq initialization
2023 struct i40iw_ccq_init_info *info)
2027 if (info->num_elem < I40IW_MIN_CQ_SIZE || info->num_elem > I40IW_MAX_CQ_SIZE)
2030 if (info->ceq_id > I40IW_MAX_CEQID)
2033 pble_obj_cnt = info->dev->hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt;
2035 if (info->virtual_map && (info->first_pm_pbl_idx >= pble_obj_cnt))
2038 cq->cq_pa = info->cq_pa;
2039 cq->cq_uk.cq_base = info->cq_base;
2040 cq->shadow_area_pa = info->shadow_area_pa;
2041 cq->cq_uk.shadow_area = info->shadow_area;
2042 cq->shadow_read_threshold = info->shadow_read_threshold;
2043 cq->dev = info->dev;
2044 cq->ceq_id = info->ceq_id;
2045 cq->cq_uk.cq_size = info->num_elem;
2047 cq->ceqe_mask = info->ceqe_mask;
2048 I40IW_RING_INIT(cq->cq_uk.cq_ring, info->num_elem);
2051 cq->ceq_id_valid = info->ceq_id_valid;
2052 cq->tph_en = info->tph_en;
2053 cq->tph_val = info->tph_val;
2054 cq->cq_uk.avoid_mem_cflct = info->avoid_mem_cflct;
2056 cq->pbl_list = info->pbl_list;
2057 cq->virtual_map = info->virtual_map;
2058 cq->pbl_chunk_size = info->pbl_chunk_size;
2059 cq->first_pm_pbl_idx = info->first_pm_pbl_idx;
2064 info->dev->ccq = cq;
2195 * @info: cq initialization info
2198 struct i40iw_cq_init_info *info)
2205 pble_obj_cnt = info->dev->hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt;
2207 if (info->virtual_map && (info->first_pm_pbl_idx >= pble_obj_cnt))
2210 cq->cq_pa = info->cq_base_pa;
2211 cq->dev = info->dev;
2212 cq->ceq_id = info->ceq_id;
2213 arm_offset = (info->dev->is_pf) ? I40E_PFPE_CQARM : I40E_VFPE_CQARM1;
2217 info->cq_uk_init_info.cqe_alloc_reg = cqe_alloc_reg;
2218 ret_code = i40iw_cq_uk_init(&cq->cq_uk, &info->cq_uk_init_info);
2221 cq->virtual_map = info->virtual_map;
2222 cq->pbl_chunk_size = info->pbl_chunk_size;
2223 cq->ceqe_mask = info->ceqe_mask;
2224 cq->cq_type = (info->type) ? info->type : I40IW_CQ_TYPE_IWARP;
2226 cq->shadow_area_pa = info->shadow_area_pa;
2227 cq->shadow_read_threshold = info->shadow_read_threshold;
2229 cq->ceq_id_valid = info->ceq_id_valid;
2230 cq->tph_en = info->tph_en;
2231 cq->tph_val = info->tph_val;
2233 cq->first_pm_pbl_idx = info->first_pm_pbl_idx;
2346 * @info: modification info struct
2351 struct i40iw_modify_cq_info *info,
2363 if (info->ceq_valid && (info->ceq_id > I40IW_MAX_CEQID))
2368 if (info->cq_resize && info->virtual_map &&
2369 (info->first_pm_pbl_idx >= pble_obj_cnt))
2377 cq->pbl_list = info->pbl_list;
2378 cq->cq_pa = info->cq_pa;
2379 cq->first_pm_pbl_idx = info->first_pm_pbl_idx;
2381 cq_size = info->cq_resize ? info->cq_size : cq->cq_uk.cq_size;
2382 if (info->ceq_change) {
2384 ceq_id = info->ceq_id;
2389 virtual_map = info->cq_resize ? info->virtual_map : cq->virtual_map;
2390 first_pm_pbl_idx = (info->cq_resize ?
2391 (info->virtual_map ? info->first_pm_pbl_idx : 0) :
2393 pbl_chunk_size = (info->cq_resize ?
2394 (info->virtual_map ? info->pbl_chunk_size : 0) :
2396 check_overflow = info->check_overflow_change ? info->check_overflow :
2409 LS_64(info->shadow_read_threshold, I40IW_CQPSQ_CQ_SHADOW_READ_THRESHOLD));
2418 LS_64(info->cq_resize, I40IW_CQPSQ_CQ_CQRESIZE) |
2441 * @info: initialization qp info
2444 struct i40iw_qp_init_info *info)
2452 qp->dev = info->pd->dev;
2453 qp->vsi = info->vsi;
2454 qp->sq_pa = info->sq_pa;
2455 qp->rq_pa = info->rq_pa;
2456 qp->hw_host_ctx_pa = info->host_ctx_pa;
2457 qp->q2_pa = info->q2_pa;
2458 qp->shadow_area_pa = info->shadow_area_pa;
2460 qp->q2_buf = info->q2;
2461 qp->pd = info->pd;
2462 qp->hw_host_ctx = info->host_ctx;
2468 info->qp_uk_init_info.wqe_alloc_reg = wqe_alloc_reg;
2469 info->qp_uk_init_info.abi_ver = qp->pd->abi_ver;
2470 ret_code = i40iw_qp_uk_init(&qp->qp_uk, &info->qp_uk_init_info);
2473 qp->virtual_map = info->virtual_map;
2475 pble_obj_cnt = info->pd->dev->hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt;
2477 if ((info->virtual_map && (info->sq_pa >= pble_obj_cnt)) ||
2478 (info->virtual_map && (info->rq_pa >= pble_obj_cnt)))
2482 qp->qp_type = (info->type) ? info->type : I40IW_QP_TYPE_IWARP;
2508 qp->sq_tph_val = info->sq_tph_val;
2509 qp->rq_tph_val = info->rq_tph_val;
2510 qp->sq_tph_en = info->sq_tph_en;
2511 qp->rq_tph_en = info->rq_tph_en;
2512 qp->rcv_tph_en = info->rcv_tph_en;
2513 qp->xmit_tph_en = info->xmit_tph_en;
2522 * @info: qp create info
2528 struct i40iw_create_qp_info *info,
2551 LS_64((info->ord_valid ? 1 : 0), I40IW_CQPSQ_QP_ORDVALID) |
2552 LS_64(info->tcp_ctx_valid, I40IW_CQPSQ_QP_TOECTXVALID) |
2555 LS_64(info->cq_num_valid, I40IW_CQPSQ_QP_CQNUMVALID) |
2556 LS_64(info->arp_cache_idx_valid, I40IW_CQPSQ_QP_ARPTABIDXVALID) |
2557 LS_64(info->next_iwarp_state, I40IW_CQPSQ_QP_NEXTIWSTATE) |
2572 * @info: modify qp info
2578 struct i40iw_modify_qp_info *info,
2592 if (info->next_iwarp_state == I40IW_QP_STATE_TERMINATE) {
2593 if (info->dont_send_fin)
2595 if (info->dont_send_term)
2599 term_len = info->termlen;
2611 LS_64(info->ord_valid, I40IW_CQPSQ_QP_ORDVALID) |
2612 LS_64(info->tcp_ctx_valid, I40IW_CQPSQ_QP_TOECTXVALID) |
2613 LS_64(info->cached_var_valid, I40IW_CQPSQ_QP_CACHEDVARVALID) |
2615 LS_64(info->cq_num_valid, I40IW_CQPSQ_QP_CQNUMVALID) |
2616 LS_64(info->force_loopback, I40IW_CQPSQ_QP_FORCELOOPBACK) |
2618 LS_64(info->remove_hash_idx, I40IW_CQPSQ_QP_REMOVEHASHENTRY) |
2620 LS_64(info->reset_tcp_conn, I40IW_CQPSQ_QP_RESETCON) |
2621 LS_64(info->arp_cache_idx_valid, I40IW_CQPSQ_QP_ARPTABIDXVALID) |
2622 LS_64(info->next_iwarp_state, I40IW_CQPSQ_QP_NEXTIWSTATE) |
2681 * @info: dlush information
2687 struct i40iw_qp_flush_info *info,
2697 if (info->rq && !qp->flush_rq)
2700 if (info->sq && !qp->flush_sq)
2712 if (info->userflushcode) {
2714 temp |= LS_64(info->rq_minor_code, I40IW_CQPSQ_FWQE_RQMNERR) |
2715 LS_64(info->rq_major_code, I40IW_CQPSQ_FWQE_RQMJERR);
2718 temp |= LS_64(info->sq_minor_code, I40IW_CQPSQ_FWQE_SQMNERR) |
2719 LS_64(info->sq_major_code, I40IW_CQPSQ_FWQE_SQMJERR);
2724 temp = (info->generate_ae) ?
2725 info->ae_code | LS_64(info->ae_source, I40IW_CQPSQ_FWQE_AESOURCE) : 0;
2731 LS_64(info->generate_ae, I40IW_CQPSQ_FWQE_GENERATE_AE) |
2732 LS_64(info->userflushcode, I40IW_CQPSQ_FWQE_USERFLCODE) |
2750 * @info: gen ae information
2756 struct i40iw_gen_ae_info *info,
2770 temp = info->ae_code |
2771 LS_64(info->ae_source, I40IW_CQPSQ_FWQE_AESOURCE);
2793 * @info: upload context info ptr for return
2799 struct i40iw_upload_context_info *info,
2811 set_64bit_val(wqe, 16, info->buf_pa);
2813 header = LS_64(info->qp_id, I40IW_CQPSQ_UCTX_QPID) |
2815 LS_64(info->qp_type, I40IW_CQPSQ_UCTX_QPTYPE) |
2816 LS_64(info->raw_format, I40IW_CQPSQ_UCTX_RAWFORMAT) |
2817 LS_64(info->freeze_qp, I40IW_CQPSQ_UCTX_FREEZEQP) |
2834 * @info: ctx info
2839 struct i40iw_qp_host_ctx_info *info)
2847 iw = info->iwarp_info;
2848 tcp = info->tcp_info;
2851 if (info->add_to_qoslist) {
2852 qp->user_pri = info->user_pri;
2858 LS_64(info->err_rq_idx_valid, I40IWQPC_ERR_RQ_IDX_VALID) |
2863 LS_64(info->push_idx, I40IWQPC_PPIDX) |
2864 LS_64(info->push_mode_en, I40IWQPC_PMENA);
2875 LS_64(info->err_rq_idx, I40IWQPC_ERR_RQ_IDX));
2879 LS_64(info->send_cq_num, I40IWQPC_TXCQNUM) |
2880 LS_64(info->rcv_cq_num, I40IWQPC_RXCQNUM));
2884 LS_64(info->qp_compl_ctx, I40IWQPC_QPCOMPCTX));
2892 if (info->iwarp_info_valid) {
2925 if (info->tcp_info_valid) {
3021 * @info: stag info
3027 struct i40iw_allocate_stag_info *info,
3036 if (!info->total_len && !info->all_memory)
3039 page_size = (info->page_size == 0x200000) ? I40IW_PAGE_SIZE_2M : I40IW_PAGE_SIZE_4K;
3046 LS_64(info->pd_id, I40IW_CQPSQ_STAG_PDID) |
3047 LS_64(info->total_len, I40IW_CQPSQ_STAG_STAGLEN));
3050 LS_64(info->stag_idx, I40IW_CQPSQ_STAG_IDX));
3053 LS_64(info->hmc_fcn_index, I40IW_CQPSQ_STAG_HMCFNIDX));
3057 LS_64(info->access_rights, I40IW_CQPSQ_STAG_ARIGHTS) |
3058 LS_64(info->chunk_size, I40IW_CQPSQ_STAG_LPBLSIZE) |
3060 LS_64(info->remote_access, I40IW_CQPSQ_STAG_REMACCENABLED) |
3061 LS_64(info->use_hmc_fcn_index, I40IW_CQPSQ_STAG_USEHMCFNIDX) |
3062 LS_64(info->use_pf_rid, I40IW_CQPSQ_STAG_USEPFRID) |
3078 * @info: mr info
3084 struct i40iw_reg_ns_stag_info *info,
3097 if (!info->total_len && !info->all_memory)
3100 page_size = (info->page_size == 0x200000) ? I40IW_PAGE_SIZE_2M : I40IW_PAGE_SIZE_4K;
3101 if (info->access_rights & (I40IW_ACCESS_FLAGS_REMOTEREAD_ONLY |
3109 if (info->chunk_size && (info->first_pm_pbl_index >= pble_obj_cnt))
3117 temp = (info->addr_type == I40IW_ADDR_TYPE_VA_BASED) ? (uintptr_t)info->va : info->fbo;
3122 LS_64(info->total_len, I40IW_CQPSQ_STAG_STAGLEN) |
3123 LS_64(info->pd_id, I40IW_CQPSQ_STAG_PDID));
3127 LS_64(info->stag_key, I40IW_CQPSQ_STAG_KEY) |
3128 LS_64(info->stag_idx, I40IW_CQPSQ_STAG_IDX));
3129 if (!info->chunk_size) {
3130 set_64bit_val(wqe, 32, info->reg_addr_pa);
3134 set_64bit_val(wqe, 48, info->first_pm_pbl_index);
3136 set_64bit_val(wqe, 40, info->hmc_fcn_index);
3139 addr_type = (info->addr_type == I40IW_ADDR_TYPE_VA_BASED) ? 1 : 0;
3142 LS_64(info->chunk_size, I40IW_CQPSQ_STAG_LPBLSIZE) |
3144 LS_64(info->access_rights, I40IW_CQPSQ_STAG_ARIGHTS) |
3147 LS_64(info->use_hmc_fcn_index, I40IW_CQPSQ_STAG_USEHMCFNIDX) |
3148 LS_64(info->use_pf_rid, I40IW_CQPSQ_STAG_USEPFRID) |
3164 * @info: info for shared memory registeration
3170 struct i40iw_register_shared_stag *info,
3181 if (info->access_rights & (I40IW_ACCESS_FLAGS_REMOTEREAD_ONLY |
3190 va64 = (uintptr_t)(info->va);
3196 (info->addr_type == I40IW_ADDR_TYPE_VA_BASED ? (uintptr_t)info->va : fbo));
3200 LS_64(info->pd_id, I40IW_CQPSQ_STAG_PDID));
3201 temp = LS_64(info->new_stag_key, I40IW_CQPSQ_STAG_KEY) |
3202 LS_64(info->new_stag_idx, I40IW_CQPSQ_STAG_IDX) |
3203 LS_64(info->parent_stag_idx, I40IW_CQPSQ_STAG_PARENTSTAGIDX);
3206 addr_type = (info->addr_type == I40IW_ADDR_TYPE_VA_BASED) ? 1 : 0;
3209 LS_64(info->access_rights, I40IW_CQPSQ_STAG_ARIGHTS) |
3227 * @info: dealloc stag info
3233 struct i40iw_dealloc_stag_info *info,
3247 LS_64(info->pd_id, I40IW_CQPSQ_STAG_PDID));
3250 LS_64(info->stag_idx, I40IW_CQPSQ_STAG_IDX));
3253 LS_64(info->mr, I40IW_CQPSQ_STAG_MR) |
3347 * @info: fast mr info
3352 struct i40iw_fast_reg_stag_info *info,
3360 page_size = (info->page_size == 0x200000) ? I40IW_PAGE_SIZE_2M : I40IW_PAGE_SIZE_4K;
3362 0, info->wr_id);
3367 __func__, info->wr_id, wqe_idx,
3369 temp = (info->addr_type == I40IW_ADDR_TYPE_VA_BASED) ? (uintptr_t)info->va : info->fbo;
3372 temp = RS_64(info->first_pm_pbl_index >> 16, I40IWQPSQ_FIRSTPMPBLIDXHI);
3376 LS_64(info->reg_addr_pa >> I40IWQPSQ_PBLADDR_SHIFT, I40IWQPSQ_PBLADDR));
3380 info->total_len |
3381 LS_64(info->first_pm_pbl_index, I40IWQPSQ_FIRSTPMPBLIDXLO));
3383 header = LS_64(info->stag_key, I40IWQPSQ_STAGKEY) |
3384 LS_64(info->stag_idx, I40IWQPSQ_STAGINDEX) |
3386 LS_64(info->chunk_size, I40IWQPSQ_LPBLSIZE) |
3388 LS_64(info->access_rights, I40IWQPSQ_STAGRIGHTS) |
3389 LS_64(info->addr_type, I40IWQPSQ_VABASEDTO) |
3390 LS_64(info->read_fence, I40IWQPSQ_READFENCE) |
3391 LS_64(info->local_fence, I40IWQPSQ_LOCALFENCE) |
3392 LS_64(info->signaled, I40IWQPSQ_SIGCOMPL) |
3630 /* parse the fpm_query_buf and fill hmc obj info */
3643 /* parse the fpm_commit_buf and fill hmc obj info */
3709 /* parse the fpm_commit_buf and fill hmc obj info */
3724 * @info; sd info for wqe
3728 struct i40iw_update_sds_info *info,
3744 wqe_entries = (info->cnt > 3) ? 3 : info->cnt;
3745 mem_entries = info->cnt - wqe_entries;
3753 memcpy((char *)sdbuf->va + offset, &info->entry[3],
3759 data |= LS_64(info->hmc_fn_id, I40IW_CQPSQ_UPESD_HMCFNID);
3766 (LS_64(info->entry[2].cmd, I40IW_CQPSQ_UPESD_SDCMD) |
3769 set_64bit_val(wqe, 56, info->entry[2].data);
3773 (LS_64(info->entry[1].cmd, I40IW_CQPSQ_UPESD_SDCMD) |
3776 set_64bit_val(wqe, 40, info->entry[1].data);
3780 LS_64(info->entry[0].cmd, I40IW_CQPSQ_UPESD_SDCMD));
3782 set_64bit_val(wqe, 8, info->entry[0].data);
3798 * @info: sd info for sd's
3802 struct i40iw_update_sds_info *info,
3808 ret_code = cqp_sds_wqe_fill(cqp, info, scratch);
3818 * @info: sd info for sd's
3821 struct i40iw_update_sds_info *info)
3827 ret_code = cqp_sds_wqe_fill(cqp, info, 0);
4126 * @pcmdinfo: cqp command info
4165 &pcmdinfo->in.u.manage_apbvt_entry.info,
4188 &pcmdinfo->in.u.add_local_mac_ipaddr_entry.info,
4195 &pcmdinfo->in.u.manage_qhash_table_entry.info,
4203 &pcmdinfo->in.u.qp_modify.info,
4211 &pcmdinfo->in.u.qp_upload_context.info,
4233 &pcmdinfo->in.u.qp_create.info,
4250 &pcmdinfo->in.u.alloc_stag.info,
4257 &pcmdinfo->in.u.mr_reg_non_shared.info,
4265 &pcmdinfo->in.u.dealloc_stag.info,
4282 &pcmdinfo->in.u.qp_flush_wqes.info,
4289 &pcmdinfo->in.u.gen_ae.info,
4296 &pcmdinfo->in.u.add_arp_cache_entry.info,
4303 &pcmdinfo->in.u.manage_push_page.info,
4311 &pcmdinfo->in.u.update_pe_sds.info,
4320 (u8)pcmdinfo->in.u.manage_hmc_pm.info.vf_id,
4321 pcmdinfo->in.u.manage_hmc_pm.info.free_fcn,
4339 &pcmdinfo->in.u.manage_vf_pble_bp.info,
4380 * @pcmdinfo: cqp command info
4421 * @info: aeq info for the packet
4424 static u32 i40iw_iwarp_opcode(struct i40iw_aeqe_info *info, u8 *pkt)
4429 if (info->q2_data_written) {
4473 * @info: the struct contiaing AE information
4476 struct i40iw_aeqe_info *info)
4488 if (info->q2_data_written) {
4517 opcode = i40iw_iwarp_opcode(info, pkt);
4519 switch (info->ae_id) {
4531 if (info->q2_data_written)
4668 * @info: the struct contiaing AE information
4670 void i40iw_terminate_connection(struct i40iw_sc_qp *qp, struct i40iw_aeqe_info *info)
4679 termlen = i40iw_bld_terminate_hdr(qp, info);
4689 * @info: the struct contiaing AE information
4691 void i40iw_terminate_received(struct i40iw_sc_qp *qp, struct i40iw_aeqe_info *info)
4701 if (info->q2_data_written) {
4718 info->ae_id = aeq_id;
4719 if (info->ae_id) {
4721 i40iw_terminate_connection(qp, info);
4741 * @info: parameters to initialize vsi
4743 void i40iw_sc_vsi_init(struct i40iw_sc_vsi *vsi, struct i40iw_vsi_init_info *info)
4747 vsi->dev = info->dev;
4748 vsi->back_vsi = info->back_vsi;
4749 vsi->mtu = info->params->mtu;
4750 vsi->exception_lan_queue = info->exception_lan_queue;
4751 i40iw_fill_qos_list(info->params->qs_handle_list);
4754 vsi->qos[i].qs_handle = info->params->qs_handle_list[i];
5068 * @info: The info structure used for initialization
5070 enum i40iw_status_code i40iw_vsi_stats_init(struct i40iw_sc_vsi *vsi, struct i40iw_vsi_stats_info *info)
5072 u8 fcn_id = info->fcn_id;
5074 if (info->alloc_fcn_id)
5080 vsi->pestat = info->pestat;
5084 if (info->stats_initialize) {
5089 vsi->stats_fcn_id_alloc = info->alloc_fcn_id;
5216 * @info: IWARP init info
5219 struct i40iw_device_init_info *info)
5231 dev->debug_mask = info->debug_mask;
5233 dev->hmc_fn_id = info->hmc_fn_id;
5234 dev->is_pf = info->is_pf;
5236 dev->fpm_query_buf_pa = info->fpm_query_buf_pa;
5237 dev->fpm_query_buf = info->fpm_query_buf;
5239 dev->fpm_commit_buf_pa = info->fpm_commit_buf_pa;
5240 dev->fpm_commit_buf = info->fpm_commit_buf;
5242 dev->hw = info->hw;
5243 dev->hw->hw_addr = info->bar0;
5275 dev->vchnl_if.vchnl_send = info->vchnl_send;