Lines Matching defs:engine
87 /* max wait time for a SDMA engine to indicate it has halted */
89 /* all SDMA engine errors that cause a halt */
303 * sdma engine 'sde' to drop to 0.
327 dd_dev_err(dd, "%s: engine %u timeout waiting for packets to egress, remaining count %u, bouncing link\n",
442 * If the engine has been brought to running during
444 * that the process of bringing the engine to running
475 "SDMA engine %d - timeout waiting for engine to halt\n",
503 "SDMA engine %d - check scheduled\n",
519 /* check progress on each engine except the current one */
744 * sdma_engine_get_vl() - return vl for a given sdma engine
745 * @sde: sdma engine
747 * This function returns the vl mapped to a given engine, or an error if
772 * sdma_select_engine_vl() - select sdma engine
778 * This function returns an engine based on the selector and a vl. The
792 * Default will return engine 0 below
816 * sdma_select_engine_sc() - select sdma engine
822 * This function returns an engine based on the selector and an sc.
859 * sdma_select_user_engine() - select sdma engine based on user setup
864 * This function returns an sdma engine for a user sdma request.
865 * User defined sdma engine affinity setting is honored when applicable,
866 * otherwise system default sdma engine mapping is used. To ensure correct
877 * To ensure that always the same sdma engine(s) will be
930 * Prevents concurrent reads and writes of the sdma engine cpu_mask
1179 * @vl_engines: per vl engine mapping (optional)
1183 * vl_engines is used to specify a non-uniform vl/engine loading. NULL
1205 int engine = 0;
1238 int first_engine = engine;
1254 &dd->per_sdma[engine];
1255 if (++engine >= first_engine + vl_engines[i])
1256 /* wrap back to first engine */
1257 engine = first_engine;
1266 engine = first_engine + vl_engines[i];
1504 /* assign each engine to different cacheline and init registers */
1887 * sdma_engine_interrupt() - interrupt handler for engine
1888 * @sde: sdma engine
1891 * Status is a mask of the 3 possible interrupts for this engine. It will
1892 * contain bits _only_ for this SDMA engine. It will contain at least one
1911 * sdma_engine_error() - error handler for engine
1912 * @sde: sdma engine
1931 "SDMA (%u) engine error: 0x%llx state %s\n",
2041 * Set the SEND_DMA_CHECK_ENABLE register for send DMA engine 'sde'.
2207 * @sde: send dma engine to dump
2382 * @sde: sdma engine to use
2448 * @sde: sdma engine to use
2454 * which are added to SDMA engine flush list if the SDMA engine state is
2587 fallthrough; /* and start dma engine */
2960 /* notify caller this engine is done cleaning */
3284 * @sde: engine to allocate from
3316 * @sde: engine to return AHG entry
3336 * This event will pull the engine out of running so no more entries can be
3337 * added to the engine's queue.
3384 * software clean will read engine CSRs, so must be completed before
3385 * the next step, which will clear the engine CSRs.
3411 * _sdma_engine_progress_schedule() - schedule progress on engine