Lines Matching defs:opcode
78 if (!e->opcode) {
158 if (e->opcode != TID_OP(WRITE_REQ) &&
180 if (e->opcode == OP(RDMA_READ_REQUEST)) {
214 } else if (e->opcode == TID_OP(WRITE_REQ)) {
229 } else if (e->opcode == TID_OP(READ_REQ)) {
337 trace_hfi1_tid_req_make_rc_ack_write(qp, 0, e->opcode, e->psn,
538 (wqe->wr.opcode != IB_WR_TID_RDMA_READ ||
547 if (wqe->wr.opcode == IB_WR_REG_MR ||
548 wqe->wr.opcode == IB_WR_LOCAL_INV) {
593 switch (wqe->wr.opcode) {
605 if (wqe->wr.opcode == IB_WR_SEND) {
607 } else if (wqe->wr.opcode == IB_WR_SEND_WITH_IMM) {
647 if (wqe->wr.opcode == IB_WR_RDMA_WRITE) {
713 if (__w->wr.opcode != IB_WR_TID_RDMA_WRITE ||
763 wqe->wr.opcode,
803 wqe->wr.opcode,
888 if (wqe->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
889 wqe->wr.opcode == IB_WR_OPFN) {
916 if (wqe->wr.opcode != IB_WR_TID_RDMA_READ) {
928 if (wqe->wr.opcode == IB_WR_RDMA_READ ||
929 wqe->wr.opcode == IB_WR_TID_RDMA_WRITE)
931 else if (wqe->wr.opcode == IB_WR_TID_RDMA_READ)
939 * qp->s_state is normally set to the opcode of the
961 if (wqe->wr.opcode == IB_WR_SEND) {
963 } else if (wqe->wr.opcode == IB_WR_SEND_WITH_IMM) {
984 * qp->s_state is normally set to the opcode of the
1006 if (wqe->wr.opcode == IB_WR_RDMA_WRITE) {
1024 * qp->s_state is normally set to the opcode of the
1074 trace_hfi1_tid_req_make_req_write(qp, 0, wqe->wr.opcode,
1079 if (wqe->wr.opcode != IB_WR_TID_RDMA_READ)
1129 trace_hfi1_tid_req_make_req_read(qp, 0, wqe->wr.opcode,
1140 if (wqe->wr.opcode != IB_WR_TID_RDMA_READ || delta == 0 ||
1172 trace_hfi1_tid_req_make_req_read(qp, 0, wqe->wr.opcode,
1179 wqe->wr.opcode != IB_WR_TID_RDMA_WRITE)
1462 u32 opcode = wqe->wr.opcode;
1464 if (opcode == IB_WR_RDMA_READ ||
1465 opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
1466 opcode == IB_WR_ATOMIC_FETCH_AND_ADD) {
1468 } else if (opcode == IB_WR_TID_RDMA_READ) {
1480 wqe->wr.opcode,
1504 u32 opcode;
1523 /* Find the work request opcode corresponding to the given PSN. */
1550 opcode = wqe->wr.opcode;
1557 switch (opcode) {
1624 if (wqe->wr.opcode == IB_WR_OPFN) {
1637 if (wqe->wr.opcode == IB_WR_TID_RDMA_READ) {
1658 if (wqe->wr.opcode == IB_WR_RDMA_READ ||
1659 wqe->wr.opcode == IB_WR_TID_RDMA_READ)
1687 if (wqe->wr.opcode == IB_WR_RDMA_READ ||
1688 wqe->wr.opcode == IB_WR_TID_RDMA_READ ||
1689 wqe->wr.opcode == IB_WR_TID_RDMA_WRITE)
1717 u8 opcode = ib_bth_get_opcode(ohdr);
1721 if ((opcode >= OP(RDMA_READ_RESPONSE_FIRST) &&
1722 opcode <= OP(ATOMIC_ACKNOWLEDGE)) ||
1723 opcode == TID_OP(READ_RESP) ||
1724 opcode == TID_OP(WRITE_RESP))
1740 u32 opcode, head, tail;
1749 opcode = ib_bth_get_opcode(ohdr);
1750 if ((opcode >= OP(RDMA_READ_RESPONSE_FIRST) &&
1751 opcode <= OP(ATOMIC_ACKNOWLEDGE)) ||
1752 opcode == TID_OP(READ_RESP) ||
1753 opcode == TID_OP(WRITE_RESP)) {
1764 if (opcode != TID_OP(WRITE_DATA) &&
1765 opcode != TID_OP(WRITE_DATA_LAST) &&
1766 opcode != TID_OP(ACK) && opcode != TID_OP(RESYNC))
1770 if (opcode >= TID_OP(WRITE_REQ) &&
1771 opcode <= TID_OP(WRITE_DATA_LAST)) {
1800 opcode != TID_OP(WRITE_DATA) && opcode != TID_OP(WRITE_DATA_LAST) &&
1801 opcode != TID_OP(RESYNC) &&
1805 if (opcode == TID_OP(READ_REQ))
1812 if ((opcode == TID_OP(WRITE_DATA) ||
1813 opcode == TID_OP(WRITE_DATA_LAST) ||
1814 opcode == TID_OP(RESYNC)) &&
1825 if (wqe->wr.opcode == IB_WR_TID_RDMA_WRITE &&
1839 ib_hfi1_wc_opcode[wqe->wr.opcode],
1885 ib_hfi1_wc_opcode[wqe->wr.opcode],
1916 if (wqe->wr.opcode != IB_WR_TID_RDMA_WRITE)
1999 * @opcode: the opcode of the request that resulted in the ACK
2006 int do_rc_ack(struct rvt_qp *qp, u32 aeth, u32 psn, int opcode,
2042 if (wqe->wr.opcode == IB_WR_RDMA_READ &&
2043 opcode == OP(RDMA_READ_RESPONSE_ONLY) &&
2057 if ((wqe->wr.opcode == IB_WR_RDMA_READ &&
2058 (opcode != OP(RDMA_READ_RESPONSE_LAST) || diff != 0)) ||
2059 (wqe->wr.opcode == IB_WR_TID_RDMA_READ &&
2060 (opcode != TID_OP(READ_RESP) || diff != 0)) ||
2061 ((wqe->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
2062 wqe->wr.opcode == IB_WR_ATOMIC_FETCH_AND_ADD) &&
2063 (opcode != OP(ATOMIC_ACKNOWLEDGE) || diff != 0)) ||
2064 (wqe->wr.opcode == IB_WR_TID_RDMA_WRITE &&
2073 if (wqe->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
2074 wqe->wr.opcode == IB_WR_ATOMIC_FETCH_AND_ADD) {
2078 if (wqe->wr.opcode == IB_WR_OPFN)
2082 (wqe->wr.opcode == IB_WR_RDMA_READ ||
2083 wqe->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
2084 wqe->wr.opcode == IB_WR_ATOMIC_FETCH_AND_ADD)) {
2103 if (wqe->wr.opcode == IB_WR_TID_RDMA_WRITE)
2116 if (wqe->wr.opcode == IB_WR_TID_RDMA_READ) {
2132 if (__w && __w->wr.opcode == IB_WR_TID_RDMA_WRITE &&
2133 opcode == TID_OP(WRITE_RESP)) {
2197 if (wqe->wr.opcode == IB_WR_TID_RDMA_WRITE &&
2198 opcode != TID_OP(WRITE_RESP) &&
2211 if (!(rdi->post_parms[wqe->wr.opcode].flags &
2227 if (wqe->wr.opcode == IB_WR_TID_RDMA_WRITE) {
2274 if (wqe->wr.opcode == IB_WR_TID_RDMA_READ)
2317 if (wqe->wr.opcode == IB_WR_RDMA_READ ||
2318 wqe->wr.opcode == IB_WR_TID_RDMA_READ ||
2319 wqe->wr.opcode == IB_WR_TID_RDMA_WRITE ||
2320 wqe->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
2321 wqe->wr.opcode == IB_WR_ATOMIC_FETCH_AND_ADD)
2361 u8 opcode = packet->opcode;
2376 if (diff == 0 && opcode == OP(ACKNOWLEDGE)) {
2399 switch (opcode) {
2404 if (opcode == OP(ATOMIC_ACKNOWLEDGE))
2408 if (!do_rc_ack(qp, aeth, psn, opcode, val, rcd) ||
2409 opcode != OP(RDMA_READ_RESPONSE_FIRST))
2412 if (unlikely(wqe->wr.opcode != IB_WR_RDMA_READ))
2427 if (unlikely(wqe->wr.opcode != IB_WR_RDMA_READ))
2445 if (opcode == OP(RDMA_READ_RESPONSE_MIDDLE))
2461 if (!do_rc_ack(qp, aeth, psn, opcode, 0, rcd))
2483 if (unlikely(wqe->wr.opcode != IB_WR_RDMA_READ))
2541 * @opcode: the opcode for this packet
2552 struct rvt_qp *qp, u32 opcode, u32 psn,
2608 switch (opcode) {
2618 if (!e || e->opcode != OP(RDMA_READ_REQUEST))
2664 if (!e || e->opcode != (u8)opcode || old_req)
2813 u32 opcode = packet->opcode;
2841 if (opcode >= OP(RDMA_READ_RESPONSE_FIRST) &&
2842 opcode <= OP(ATOMIC_ACKNOWLEDGE)) {
2850 if (rc_rcv_error(ohdr, data, qp, opcode, psn, diff, rcd))
2855 /* Check for opcode sequence errors. */
2859 if (opcode == OP(SEND_MIDDLE) ||
2860 opcode == OP(SEND_LAST) ||
2861 opcode == OP(SEND_LAST_WITH_IMMEDIATE) ||
2862 opcode == OP(SEND_LAST_WITH_INVALIDATE))
2868 if (opcode == OP(RDMA_WRITE_MIDDLE) ||
2869 opcode == OP(RDMA_WRITE_LAST) ||
2870 opcode == OP(RDMA_WRITE_LAST_WITH_IMMEDIATE))
2875 if (opcode == OP(SEND_MIDDLE) ||
2876 opcode == OP(SEND_LAST) ||
2877 opcode == OP(SEND_LAST_WITH_IMMEDIATE) ||
2878 opcode == OP(SEND_LAST_WITH_INVALIDATE) ||
2879 opcode == OP(RDMA_WRITE_MIDDLE) ||
2880 opcode == OP(RDMA_WRITE_LAST) ||
2881 opcode == OP(RDMA_WRITE_LAST_WITH_IMMEDIATE))
2895 switch (opcode) {
2939 if (opcode == OP(SEND_ONLY))
2941 if (opcode == OP(SEND_ONLY_WITH_INVALIDATE))
2981 if (opcode == OP(RDMA_WRITE_LAST_WITH_IMMEDIATE) ||
2982 opcode == OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE))
2983 wc.opcode = IB_WC_RECV_RDMA_WITH_IMM;
2985 wc.opcode = IB_WC_RECV;
3040 if (opcode == OP(RDMA_WRITE_FIRST))
3042 else if (opcode == OP(RDMA_WRITE_ONLY))
3098 e->opcode = opcode;
3109 qp->r_state = opcode;
3128 bool opfn = opcode == OP(COMPARE_SWAP) &&
3166 e->atomic_data = (opcode == OP(FETCH_ADD)) ?
3174 e->opcode = opcode;
3180 qp->r_state = opcode;
3200 qp->r_state = opcode;
3257 u32 opcode;
3264 opcode = ib_bth_get_opcode(packet->ohdr);
3267 if (opcode < IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST) {