Lines Matching refs:read_csr
1342 * read_csr - read CSR at the indicated offset
1349 u64 read_csr(const struct hfi1_devdata *dd, u32 offset)
1397 ret = read_csr(dd, csr);
5268 mask = read_csr(rcd->dd, CCE_INT_MASK + (8 * (is / 64)));
5719 u64 src = read_csr(dd, SEND_EGRESS_ERR_SOURCE); /* read first */
5720 u64 info = read_csr(dd, SEND_EGRESS_ERR_INFO);
6382 reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_1);
6410 (void)read_csr(dd, DCC_CFG_RESET);
6437 u64 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
6452 u64 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
6525 dd->lcb_err_en = read_csr(dd, DC_LCB_ERR_EN);
6526 reg = read_csr(dd, DCC_CFG_RESET);
6529 (void)read_csr(dd, DCC_CFG_RESET); /* make sure the write completed */
6758 rcvctrl = read_csr(dd, RCV_CTRL);
6829 reg = read_csr(dd, CCE_STATUS);
7543 reg = read_csr(dd, SEND_CM_CTRL);
7606 reg = read_csr(dd, DC_LCB_CFG_LINK_KILL_EN);
7780 info = read_csr(dd, DC_DC8051_DBG_ERR_INFO_SET_BY_8051);
7885 read_csr(dd, DC_DC8051_ERR_EN) &
7975 info = read_csr(dd, DCC_ERR_INFO_UNCORRECTABLE);
7994 info = read_csr(dd, DCC_ERR_INFO_FMCONFIG);
8045 info = read_csr(dd, DCC_ERR_INFO_PORTRCV);
8046 hdr0 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR0);
8047 hdr1 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR1);
8343 regs[i] = read_csr(dd, CCE_INT_STATUS + (8 * i)) &
8374 /* This read_csr is really bad in the hot path */
8375 status = read_csr(dd,
8405 (void)read_csr(dd, addr);
8582 reg = read_csr(dd, DC_DC8051_STS_CUR_STATE);
8591 reg = read_csr(dd, DCC_CFG_PORT_CONFIG);
8600 reg = read_csr(dd, DCC_CFG_PORT_CONFIG);
8617 *data = read_csr(dd, addr);
8697 *data = read_csr(dd, addr);
8809 reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_0);
8833 reg = read_csr(dd, DC_DC8051_CFG_HOST_CMD_1);
8853 *out_data |= (read_csr(dd, DC_DC8051_CFG_EXT_DEV_1)
9310 (read_csr(dd, DC_DC8051_CFG_MODE) | DISABLE_SELF_GUID_CHECK));
9527 mask = read_csr(dd, dd->hfi1_id ?
9545 mask = read_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK);
9571 qsfp_mask = read_csr(dd,
10202 len1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG);
10215 u64 c1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG1);
10387 reg = read_csr(dd, DC_LCB_STS_LINK_TRANSFER_ACTIVE);
10418 (void)read_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET);
10690 reg = read_csr(ppd->dd, SEND_CM_CREDIT_VL + (8 * i));
11216 u64 reg = read_csr(dd, csr);
11245 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
11262 reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_15_0);
11270 reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_31_16);
11344 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
11355 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
11372 reg = read_csr(dd, addr);
11389 reg = read_csr(dd, addr);
11404 reg = read_csr(dd, SEND_CM_CREDIT_USED_STATUS) & mask;
13197 reg = read_csr(dd, ASIC_STS_THERM);
13229 reg = read_csr(dd, CCE_INT_MASK + (8 * idx));
13322 reg = read_csr(dd, CCE_INT_MAP + (8 * m));
13645 reg = read_csr(dd, CCE_STATUS);
13655 reg = read_csr(dd, CCE_STATUS);
13873 reg = read_csr(dd, RCV_STATUS);
13902 read_csr(dd, RCV_CTRL);
13909 reg = read_csr(dd, RCV_STATUS);
14099 (void)read_csr(dd, CCE_DC_CTRL);
14203 u64 reg = read_csr(dd, RCV_QP_MAP_TABLE + (idx / 8) * 8);
14311 return read_csr(dd, RCV_RSM_CFG + (8 * rule_index)) != 0;
14582 reg = read_csr(dd, regoff);
14599 reg = read_csr(dd, regoff);
14717 val = read_csr(dd, RCV_BYPASS);
15002 mask = read_csr(dd, CCE_INT_MASK);
15004 reg = read_csr(dd, CCE_INT_MASK);
15010 reg = read_csr(dd, CCE_INT_STATUS);
15016 reg = read_csr(dd, CCE_INT_STATUS);
15134 reg = read_csr(dd, CCE_REVISION2);