Lines Matching defs:write_csr
1357 * write_csr - write CSR at the indicated offset
1362 void write_csr(const struct hfi1_devdata *dd, u32 offset, u64 value)
1399 write_csr(dd, csr, value);
5724 write_csr(dd, SEND_EGRESS_ERR_INFO, info);
6140 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT :
6176 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT :
6231 write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL,
6242 write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL,
6365 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0,
6387 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, 0);
6408 write_csr(dd, DCC_CFG_RESET, LCB_RX_FPE_TX_FPE_INTO_RESET);
6414 write_csr(dd, DCC_CFG_RESET, LCB_RX_FPE_TX_FPE_OUT_OF_RESET);
6442 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
6463 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
6465 write_csr(dd, SEND_CM_CREDIT_VL15, (u64)vl15buf
6479 write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0);
6480 write_csr(dd, SEND_CM_CREDIT_VL15, 0);
6481 write_csr(dd, SEND_CM_GLOBAL_CREDIT, 0);
6520 write_csr(dd, DC_LCB_CFG_RUN, 0);
6522 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET,
6527 write_csr(dd, DCC_CFG_RESET, reg |
6532 write_csr(dd, DCC_CFG_RESET, reg);
6533 write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en);
6562 write_csr(dd, DC_DC8051_CFG_RST, 0x1);
6586 write_csr(dd, DC_DC8051_CFG_RST, 0ull);
6593 write_csr(dd, DCC_CFG_RESET, LCB_RX_FPE_TX_FPE_OUT_OF_RESET);
6595 write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en);
6673 write_csr(dd, DC_LCB_CFG_LN_DCLK, 1ull);
6684 write_csr(dd, DC_LCB_CFG_RX_FIFOS_RADR, rx_radr);
6686 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK,
6688 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RADR, tx_radr);
6761 write_csr(dd, RCV_CTRL, rcvctrl);
6786 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK);
6935 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK);
6939 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK);
6941 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK);
7539 write_csr(dd, DC_LCB_CFG_CRC_MODE,
7545 write_csr(dd, SEND_CM_CTRL,
7548 write_csr(dd, SEND_CM_CTRL,
7609 write_csr(dd, DC_LCB_CFG_LINK_KILL_EN, reg);
7613 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0);
7616 write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */
7884 write_csr(dd, DC_DC8051_ERR_EN,
8347 write_csr(dd, CCE_INT_CLEAR + (8 * i), regs[i]);
8380 write_csr(dd,
8403 write_csr(dd, addr, rcd->imask);
8411 write_csr(rcd->dd, CCE_INT_FORCE + (8 * rcd->ireg), rcd->imask);
8604 write_csr(dd, DCC_CFG_PORT_CONFIG, reg);
8712 write_csr(dd, addr, data);
8742 write_csr(dd, addr, data);
8815 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, reg);
8826 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg);
8828 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg);
8865 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, 0);
9239 write_csr(dd, DC_LCB_CFG_LOOPBACK,
9241 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0);
9246 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0);
9251 write_csr(dd, DC_LCB_CFG_RUN,
9258 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP,
9276 write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */
9291 write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */
9309 write_csr(dd, DC_DC8051_CFG_MODE,
9551 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR,
9557 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK, mask);
9574 write_csr(dd,
9580 write_csr(dd,
9768 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR,
9770 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK,
9778 write_csr(dd,
9801 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x01);
9802 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0x00);
9803 write_csr(dd, DC_LCB_CFG_REINIT_AS_SLAVE, 0x00);
9804 write_csr(dd, DC_LCB_CFG_CNT_FOR_SKIP_STALL, 0x110);
9805 write_csr(dd, DC_LCB_CFG_CLK_CNTR, 0x08);
9806 write_csr(dd, DC_LCB_CFG_LOOPBACK, 0x02);
9807 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x00);
10179 write_csr(dd, SEND_LEN_CHECK0, len1);
10180 write_csr(dd, SEND_LEN_CHECK1, len2);
10206 write_csr(ppd->dd, DCC_CFG_PORT_CONFIG, len1);
10229 write_csr(ppd->dd, DCC_CFG_PORT_CONFIG1, c1);
10408 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 1);
10409 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK,
10412 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0);
10413 write_csr(dd, DC_LCB_CFG_REINIT_AS_SLAVE, 0);
10414 write_csr(dd, DC_LCB_CFG_CNT_FOR_SKIP_STALL, 0x110);
10415 write_csr(dd, DC_LCB_CFG_LOOPBACK, 0x2);
10417 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0);
10420 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 1);
10421 write_csr(dd, DC_LCB_CFG_RUN, 1ull << DC_LCB_CFG_RUN_EN_SHIFT);
10428 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 1);
10429 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 0);
10430 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK, 0);
10505 write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */
10861 write_csr(dd, DCC_CFG_LED_CNTRL, 0);
11025 write_csr(ppd->dd, SEND_HIGH_PRIORITY_LIMIT, reg);
11197 write_csr(dd, target + (i * 8), reg);
11293 write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0,
11311 write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16,
11347 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
11358 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
11375 write_csr(dd, addr, reg);
11392 write_csr(dd, addr, reg);
12115 write_csr(dd, RCV_VL15, HFI1_CTRL_CTXT);
12118 write_csr(dd, RCV_VL15, 0);
13234 write_csr(dd, CCE_INT_MASK + (8 * idx), reg);
13281 write_csr(dd, CCE_INT_CLEAR + (8 * i), ~(u64)0);
13283 write_csr(dd, CCE_ERR_CLEAR, ~(u64)0);
13284 write_csr(dd, MISC_ERR_CLEAR, ~(u64)0);
13285 write_csr(dd, RCV_ERR_CLEAR, ~(u64)0);
13286 write_csr(dd, SEND_ERR_CLEAR, ~(u64)0);
13287 write_csr(dd, SEND_PIO_ERR_CLEAR, ~(u64)0);
13288 write_csr(dd, SEND_DMA_ERR_CLEAR, ~(u64)0);
13289 write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~(u64)0);
13295 write_csr(dd, DCC_ERR_FLG_CLR, ~(u64)0);
13296 write_csr(dd, DC_LCB_ERR_CLR, ~(u64)0);
13297 write_csr(dd, DC_DC8051_ERR_CLR, ~(u64)0);
13325 write_csr(dd, CCE_INT_MAP + (8 * m), reg);
13356 write_csr(dd, CCE_INT_MAP + (8 * i), 0);
13579 write_csr(dd, RCV_PARTITION_KEY +
13603 write_csr(dd, CCE_INT_MAP + (8 * i), 0);
13632 write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0);
13650 write_csr(dd, CCE_CTRL, ctrl_bits);
13681 write_csr(dd, CCE_SCRATCH + (8 * i), 0);
13683 write_csr(dd, CCE_ERR_MASK, 0);
13684 write_csr(dd, CCE_ERR_CLEAR, ~0ull);
13687 write_csr(dd, CCE_COUNTER_ARRAY32 + (8 * i), 0);
13688 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_RESETCSR);
13691 write_csr(dd, CCE_MSIX_TABLE_LOWER + (8 * i), 0);
13692 write_csr(dd, CCE_MSIX_TABLE_UPPER + (8 * i),
13697 write_csr(dd, CCE_MSIX_INT_GRANTED, ~0ull);
13698 write_csr(dd, CCE_MSIX_VEC_CLR_WITHOUT_INT, ~0ull);
13701 write_csr(dd, CCE_INT_MAP, 0);
13704 write_csr(dd, CCE_INT_MASK + (8 * i), 0);
13705 write_csr(dd, CCE_INT_CLEAR + (8 * i), ~0ull);
13710 write_csr(dd, CCE_INT_COUNTER_ARRAY32 + (8 * i), 0);
13719 write_csr(dd, MISC_CFG_RSA_R2 + (8 * i), 0);
13720 write_csr(dd, MISC_CFG_RSA_SIGNATURE + (8 * i), 0);
13721 write_csr(dd, MISC_CFG_RSA_MODULUS + (8 * i), 0);
13728 write_csr(dd, MISC_CFG_RSA_CMD, 1);
13729 write_csr(dd, MISC_CFG_RSA_MU, 0);
13730 write_csr(dd, MISC_CFG_FW_CTRL, 0);
13736 write_csr(dd, MISC_ERR_MASK, 0);
13737 write_csr(dd, MISC_ERR_CLEAR, ~0ull);
13749 write_csr(dd, SEND_CTRL, 0);
13755 write_csr(dd, SEND_HIGH_PRIORITY_LIMIT, 0);
13758 write_csr(dd, SEND_PIO_ERR_MASK, 0);
13759 write_csr(dd, SEND_PIO_ERR_CLEAR, ~0ull);
13762 write_csr(dd, SEND_DMA_ERR_MASK, 0);
13763 write_csr(dd, SEND_DMA_ERR_CLEAR, ~0ull);
13766 write_csr(dd, SEND_EGRESS_ERR_MASK, 0);
13767 write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~0ull);
13769 write_csr(dd, SEND_BTH_QP, 0);
13770 write_csr(dd, SEND_STATIC_RATE_CONTROL, 0);
13771 write_csr(dd, SEND_SC2VLT0, 0);
13772 write_csr(dd, SEND_SC2VLT1, 0);
13773 write_csr(dd, SEND_SC2VLT2, 0);
13774 write_csr(dd, SEND_SC2VLT3, 0);
13775 write_csr(dd, SEND_LEN_CHECK0, 0);
13776 write_csr(dd, SEND_LEN_CHECK1, 0);
13778 write_csr(dd, SEND_ERR_MASK, 0);
13779 write_csr(dd, SEND_ERR_CLEAR, ~0ull);
13782 write_csr(dd, SEND_LOW_PRIORITY_LIST + (8 * i), 0);
13784 write_csr(dd, SEND_HIGH_PRIORITY_LIST + (8 * i), 0);
13786 write_csr(dd, SEND_CONTEXT_SET_CTRL + (8 * i), 0);
13788 write_csr(dd, SEND_COUNTER_ARRAY32 + (8 * i), 0);
13790 write_csr(dd, SEND_COUNTER_ARRAY64 + (8 * i), 0);
13791 write_csr(dd, SEND_CM_CTRL, SEND_CM_CTRL_RESETCSR);
13792 write_csr(dd, SEND_CM_GLOBAL_CREDIT, SEND_CM_GLOBAL_CREDIT_RESETCSR);
13794 write_csr(dd, SEND_CM_TIMER_CTRL, 0);
13795 write_csr(dd, SEND_CM_LOCAL_AU_TABLE0_TO3, 0);
13796 write_csr(dd, SEND_CM_LOCAL_AU_TABLE4_TO7, 0);
13797 write_csr(dd, SEND_CM_REMOTE_AU_TABLE0_TO3, 0);
13798 write_csr(dd, SEND_CM_REMOTE_AU_TABLE4_TO7, 0);
13800 write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0);
13801 write_csr(dd, SEND_CM_CREDIT_VL15, 0);
13806 write_csr(dd, SEND_EGRESS_ERR_INFO, ~0ull);
13894 write_csr(dd, RCV_CTRL, RCV_CTRL_RX_RBUF_INIT_SMASK);
13931 write_csr(dd, RCV_CTRL, 0);
13937 write_csr(dd, RCV_BTH_QP, 0);
13938 write_csr(dd, RCV_MULTICAST, 0);
13939 write_csr(dd, RCV_BYPASS, 0);
13940 write_csr(dd, RCV_VL15, 0);
13942 write_csr(dd, RCV_ERR_INFO,
13945 write_csr(dd, RCV_ERR_MASK, 0);
13946 write_csr(dd, RCV_ERR_CLEAR, ~0ull);
13949 write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0);
13951 write_csr(dd, RCV_PARTITION_KEY + (8 * i), 0);
13953 write_csr(dd, RCV_COUNTER_ARRAY32 + (8 * i), 0);
13955 write_csr(dd, RCV_COUNTER_ARRAY64 + (8 * i), 0);
13959 write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), 0);
14009 write_csr(dd, SEND_SC2VLT0, SC2VL_VAL(
14015 write_csr(dd, SEND_SC2VLT1, SC2VL_VAL(
14021 write_csr(dd, SEND_SC2VLT2, SC2VL_VAL(
14027 write_csr(dd, SEND_SC2VLT3, SC2VL_VAL(
14035 write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0, DC_SC_VL_VAL(
14039 write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16, DC_SC_VL_VAL(
14079 write_csr(dd, SEND_CTRL, 0);
14085 write_csr(dd, RCV_CTRL, 0);
14087 write_csr(dd, RCV_CTXT_CTRL, 0);
14090 write_csr(dd, CCE_INT_MASK + (8 * i), 0ull);
14098 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK);
14138 write_csr(dd, CCE_DC_CTRL, 0);
14153 write_csr(dd, ASIC_QSFP1_OUT, 0x1f);
14154 write_csr(dd, ASIC_QSFP2_OUT, 0x1f);
14187 write_csr(dd, SEND_BTH_QP,
14191 write_csr(dd, RCV_BTH_QP,
14241 write_csr(dd, regno, reg);
14301 write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), rmt->map[i]);
14320 write_csr(dd, RCV_RSM_CFG + (8 * rule_index),
14324 write_csr(dd, RCV_RSM_SELECT + (8 * rule_index),
14331 write_csr(dd, RCV_RSM_MATCH + (8 * rule_index),
14343 write_csr(dd, RCV_RSM_CFG + (8 * rule_index), 0);
14344 write_csr(dd, RCV_RSM_SELECT + (8 * rule_index), 0);
14345 write_csr(dd, RCV_RSM_MATCH + (8 * rule_index), 0);
14596 write_csr(dd, regoff, reg);
14690 write_csr(dd, RCV_ERR_MASK, ~0ull);
14721 write_csr(dd, RCV_BYPASS, val);
14728 write_csr(dd, CCE_ERR_MASK, ~0ull);
14730 write_csr(dd, MISC_ERR_MASK, DRIVER_MISC_MASK);
14732 write_csr(dd, DCC_ERR_FLG_EN, ~0ull);
14733 write_csr(dd, DC_DC8051_ERR_EN, ~0ull);
14747 write_csr(dd, csr0to3,
14754 write_csr(dd, csr4to7,
14782 write_csr(dd, SEND_PIO_ERR_MASK, ~0ull);
14783 write_csr(dd, SEND_DMA_ERR_MASK, ~0ull);
14784 write_csr(dd, SEND_ERR_MASK, ~0ull);
14785 write_csr(dd, SEND_EGRESS_ERR_MASK, ~0ull);
14801 write_csr(dd, SEND_CM_TIMER_CTRL, HFI1_CREDIT_RETURN_RATE);
15003 write_csr(dd, CCE_INT_MASK, 0ull);
15009 write_csr(dd, CCE_INT_CLEAR, all_bits);
15015 write_csr(dd, CCE_INT_FORCE, all_bits);
15021 write_csr(dd, CCE_INT_CLEAR, all_bits);
15022 write_csr(dd, CCE_INT_MASK, mask);
15026 write_csr(dd, CCE_INT_MASK, mask);
15453 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0);
15496 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1);