Lines Matching defs:set
5752 * multiple bits set in the info register are due to a
6131 * We don't set cache_refresh_required here as we expect
6352 * to this routine to be after all LCB set-up is done. In particular, after
6454 /* set initial values for total and shared credit limit */
6521 /* set tx fifo reset: LCB_CFG_TX_FIFOS_RESET.VAL = 1 */
6524 /* set dcc reset csr: DCC_CFG_RESET.{reset_lcb,reset_rx_fpe} = 1 */
6592 /* Take away reset for LCB and RX FPE (set in lcb_shutdown). */
6740 "%s: received Active SMA idle message, couldn't set link to Active\n",
6831 /* waiting until all indicators are set */
6893 /* HFI1_RCVCTRL_TAILUPD_[ENB|DIS] needs to be set explicitly */
7022 * And (re)set link up default values.
7028 * In case of quick linkup or simulator, vl15 value will be set by
7311 * Simulator and quick linkup do not set the width.
7312 * Just set it to 4x without complaint.
7368 * Set link_speed_active here, overriding what was set in
7370 * set the max_rate field in handle_verify_cap until v0.19.
7520 * credits value and wait for link-up interrupt ot set it.
7525 /* set up the LCB CRC mode */
7542 /* set (14b only) or clear sideband credit */
7593 /* set up the remote credit return table */
7635 * link_downgraded variable is set by refresh_widths and
7778 /* 8051 information set by firmware */
7831 * this flag will still be set.
7977 /* set status bit */
7997 /* set status bit */
8052 /* set status bit */
8345 /* only clear if anything is set */
8387 dd_dev_info_ratelimited(dd, "SDMA engine %u interrupt, but no status bits set\n",
8522 WARN_ONCE(1, "Napi IRQ handler without napi set up ctxt=%d\n",
8601 /* clear current state, set new state */
8897 * set the result, even on error.
9012 /* Clear, then set field */
9265 * sides must be done with LCB set-up before either
9268 * done with LCB set up before resuming.
9271 "Pausing for peer to be finished with LCB set up\n");
9287 "%s: set physical link state to quick LinkUp failed with return %d\n",
9302 * Do all special steps to set up loopback.
9393 /* set the local tx rate - need to read-modify-write */
9400 /* set the tx rate to the fastest enabled */
9406 /* set the tx rate to all enabled */
9423 "Failed to set host interface version, return 0x%x\n",
9471 "Failed to set local link attributes, return 0x%x\n",
9800 /* set LCB for cclk loopback on the port */
10127 * HFI allows this to be set per-receive context, but the
10232 * Iterate over all the send contexts and set their SLID check
10441 * LinkDownReasons only set if transition succeeds.
10676 * are both set.
10794 * After link up, a new link width will have been set.
10827 * so neighbor_normal is not set. Set it here when we first
11045 * field set, so simply ANDing with supported has the desired result.
11047 case HFI1_IB_CFG_LWID_ENB: /* set allowed Link-width */
11050 case HFI1_IB_CFG_LWID_DG_ENB: /* set allowed link width downgrade */
11174 * set to 0 could get stuck in a FIFO with no chance to
11361 /* set the given per-VL shared limit */
11378 /* set the given per-VL dedicated limit */
11431 * set Global_Shared_Credit_Limit = 0
11434 * set Shared_Limit[mask0] = 0
11444 * lower = if the new limit is lower, set the limit to the new value
11446 * earlier in the algorithm), set the new limit to the new value
12007 * set_hdrq_regs - set header queue registers for context
12085 /* zero RcvHdrHead - set RcvHdrHead.Counter after enable */
12092 /* set eager count and base index */
12103 * rcd->expected_count is set to individual RcvArray entries,
12201 * The interrupt timeout and count must be set after
12204 /* set interrupt timeout */
12209 /* set RcvHdrHead.Counter, zero RcvHdrHead.Head (again) */
12217 * been cleared, set the RCV_HDR_TAIL_ADDR CSR to dummy address
12545 * Rather than keep beating on the CSRs pick a minimal set that we can
12647 /* set up the stats timer; the add_timer is done at the end */
12979 * Always set the flags due to the fact that the cache value
13172 u8 set = (sc->type == SC_USER ?
13177 if (set)
13215 * read_mod_write() - Calculate the IRQ register index and set/clear the bits
13218 * @bits: the bits to set or clear
13219 * @set: true == set the bits, false == clear the bits
13223 bool set)
13230 if (set)
13241 * @first: first IRQ source to set/clear
13242 * @last: last IRQ source (inclusive) to set/clear
13243 * @set: true == set the bits, false == clear the bits
13245 * If first == last, set the exact source.
13247 int set_intr_bits(struct hfi1_devdata *dd, u16 first, u16 last, bool set)
13263 read_mod_write(dd, src - 1, bits, set);
13268 read_mod_write(dd, last, bits, set);
13585 /* Always enable HW pkeys check when pkeys table is set */
13591 * written before reading to set the ECC/parity bits.
13668 /* set CCE CSRs to chip reset defaults */
13713 /* set MISC CSRs to chip reset defaults */
13741 /* set TXE CSRs to chip reset defaults */
13916 "%s: RcvStatus.RxRbufInit not set, continuing\n",
13923 /* set RXE CSRs to chip reset defaults */
13996 * they need to be set:
14696 /* set up QOS, including the QPN map table */
14708 * invalid configuration: RcvCtrl.RcvWcb set to its max of 256 and
14709 * Max_PayLoad_Size set to its minimum of 128.
14793 /* set the local CU to AU mapping */
14798 * Don't set on Simulator - causes it to choke.
14954 /* first one through - set up i2c devices */
14991 * is set up properly.
15036 * This is global, and is called directly at init to set up the
15085 * Set the initial values to reasonable default, will be set
15148 /* give a reasonable active value, will be set on link up */
15174 * Must be after icode is set up - the cclock rate depends
15188 /* set up shared ASIC data with peer device */
15264 /* set initial RXE CSRs */
15269 /* set initial TXE CSRs */
15271 /* set initial non-RXE, non-TXE CSRs */
15273 /* set up KDETH QP prefix in both RX and TX CSRs */
15280 /* send contexts must be set up before receive contexts */
15315 /* set up LCB access - must be after set_up_interrupts() */
15501 THERM_FAILURE(dd, ret, "Unable to set thermal init flag");