Lines Matching defs:rcd
5261 /* return true is kernel urg disabled for rcd */
5262 bool is_urg_masked(struct hfi1_ctxtdata *rcd)
5265 u32 is = IS_RCVURGENT_START + rcd->ctxt;
5268 mask = read_csr(rcd->dd, CCE_INT_MASK + (8 * (is / 64)));
6857 struct hfi1_ctxtdata *rcd;
6864 rcd = hfi1_rcd_get_by_index(dd, i);
6865 hfi1_rcvctrl(dd, HFI1_RCVCTRL_CTXT_DIS, rcd);
6866 hfi1_rcd_put(rcd);
6880 struct hfi1_ctxtdata *rcd;
6884 rcd = hfi1_rcd_get_by_index(dd, i);
6887 if (!rcd ||
6888 (i >= dd->first_dyn_alloc_ctxt && !rcd->is_vnic)) {
6889 hfi1_rcd_put(rcd);
6894 rcvmask |= hfi1_rcvhdrtail_kvaddr(rcd) ?
6896 hfi1_rcvctrl(dd, rcvmask, rcd);
6897 hfi1_rcd_put(rcd);
8209 struct hfi1_ctxtdata *rcd;
8213 rcd = hfi1_rcd_get_by_index(dd, source);
8214 if (rcd) {
8215 handle_user_interrupt(rcd);
8216 hfi1_rcd_put(rcd);
8219 /* received an interrupt, but no rcd */
8240 struct hfi1_ctxtdata *rcd;
8244 rcd = hfi1_rcd_get_by_index(dd, source);
8245 if (rcd) {
8246 handle_user_interrupt(rcd);
8247 hfi1_rcd_put(rcd);
8250 /* received an interrupt, but no rcd */
8398 static inline void clear_recv_intr(struct hfi1_ctxtdata *rcd)
8400 struct hfi1_devdata *dd = rcd->dd;
8401 u32 addr = CCE_INT_CLEAR + (8 * rcd->ireg);
8403 write_csr(dd, addr, rcd->imask);
8409 void force_recv_intr(struct hfi1_ctxtdata *rcd)
8411 write_csr(rcd->dd, CCE_INT_FORCE + (8 * rcd->ireg), rcd->imask);
8424 static inline int check_packet_present(struct hfi1_ctxtdata *rcd)
8428 if (hfi1_packet_present(rcd))
8432 tail = (u32)read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_TAIL);
8433 return hfi1_rcd_head(rcd) != tail;
8441 static void receive_interrupt_common(struct hfi1_ctxtdata *rcd)
8443 struct hfi1_devdata *dd = rcd->dd;
8445 trace_hfi1_receive_interrupt(dd, rcd);
8447 aspm_ctx_disable(rcd);
8455 * @rcd: valid receive context
8457 static void __hfi1_rcd_eoi_intr(struct hfi1_ctxtdata *rcd)
8459 if (!rcd->rcvhdrq)
8461 clear_recv_intr(rcd);
8462 if (check_packet_present(rcd))
8463 force_recv_intr(rcd);
8469 * @rcd: Ptr to hfi1_ctxtdata of receive context
8478 static void hfi1_rcd_eoi_intr(struct hfi1_ctxtdata *rcd)
8483 __hfi1_rcd_eoi_intr(rcd);
8496 struct hfi1_ctxtdata *rcd = rxq->rcd;
8499 work_done = rcd->do_interrupt(rcd, budget);
8503 hfi1_rcd_eoi_intr(rcd);
8512 struct hfi1_ctxtdata *rcd = data;
8514 receive_interrupt_common(rcd);
8516 if (likely(rcd->napi)) {
8517 if (likely(napi_schedule_prep(rcd->napi)))
8518 __napi_schedule_irqoff(rcd->napi);
8520 __hfi1_rcd_eoi_intr(rcd);
8523 rcd->ctxt);
8524 __hfi1_rcd_eoi_intr(rcd);
8540 struct hfi1_ctxtdata *rcd = data;
8543 receive_interrupt_common(rcd);
8546 disposition = rcd->do_interrupt(rcd, 0);
8556 __hfi1_rcd_eoi_intr(rcd);
8566 struct hfi1_ctxtdata *rcd = data;
8569 (void)rcd->do_interrupt(rcd, 1);
8571 hfi1_rcd_eoi_intr(rcd);
10010 void hfi1_clear_tids(struct hfi1_ctxtdata *rcd)
10012 struct hfi1_devdata *dd = rcd->dd;
10016 for (i = rcd->eager_base; i < rcd->eager_base +
10017 rcd->egrbufs.alloced; i++)
10020 for (i = rcd->expected_base;
10021 i < rcd->expected_base + rcd->expected_count; i++)
10137 * dd->rcd[0].rcvhdrqentsize is in DW.
10138 * We use rcd[0] as all context will have the same value. Also,
10142 return (get_hdrqentsize(dd->rcd[0]) - 2/*PBC/RHF*/ + 1/*ICRC*/) << 2;
10187 get_hdrqentsize(dd->rcd[0])));
10196 dd->rcd[0]->rcvhdrqentsize));
11841 static void adjust_rcv_timeout(struct hfi1_ctxtdata *rcd, u32 npkts)
11843 struct hfi1_devdata *dd = rcd->dd;
11844 u32 timeout = rcd->rcvavail_timeout;
11873 rcd->rcvavail_timeout = timeout;
11878 write_kctxt_csr(dd, rcd->ctxt, RCV_AVAIL_TIME_OUT,
11883 void update_usrhead(struct hfi1_ctxtdata *rcd, u32 hd, u32 updegr, u32 egrhd,
11886 struct hfi1_devdata *dd = rcd->dd;
11888 u32 ctxt = rcd->ctxt;
11895 adjust_rcv_timeout(rcd, npkts);
11907 u32 hdrqempty(struct hfi1_ctxtdata *rcd)
11911 head = (read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_HEAD)
11914 if (hfi1_rcvhdrtail_kvaddr(rcd))
11915 tail = get_rcvhdrtail(rcd);
11917 tail = read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_TAIL);
12037 struct hfi1_ctxtdata *rcd)
12043 if (!rcd)
12046 ctxt = rcd->ctxt;
12056 rcd->rcvhdrq_dma);
12057 if (hfi1_rcvhdrtail_kvaddr(rcd))
12059 rcd->rcvhdrqtailaddr_dma);
12060 hfi1_set_seq_cnt(rcd, 1);
12063 hfi1_set_rcd_head(rcd, 0);
12069 * E.g. a rcd restart before the receive header wrapped.
12071 memset(rcd->rcvhdrq, 0, rcvhdrq_size(rcd));
12074 rcd->rcvavail_timeout = dd->rcv_intr_timeout_csr;
12081 rcvctrl |= ((u64)encoded_size(rcd->egrbufs.rcvtid_size)
12093 reg = (((u64)(rcd->egrbufs.alloced >> RCV_SHIFT)
12096 (((rcd->eager_base >> RCV_SHIFT)
12103 * rcd->expected_count is set to individual RcvArray entries,
12107 reg = (((rcd->expected_count >> RCV_SHIFT)
12110 (((rcd->expected_base >> RCV_SHIFT)
12134 set_intr_bits(dd, IS_RCVAVAIL_START + rcd->ctxt,
12135 IS_RCVAVAIL_START + rcd->ctxt, true);
12139 set_intr_bits(dd, IS_RCVAVAIL_START + rcd->ctxt,
12140 IS_RCVAVAIL_START + rcd->ctxt, false);
12143 if ((op & HFI1_RCVCTRL_TAILUPD_ENB) && hfi1_rcvhdrtail_kvaddr(rcd))
12173 set_intr_bits(dd, IS_RCVURGENT_START + rcd->ctxt,
12174 IS_RCVURGENT_START + rcd->ctxt, true);
12176 set_intr_bits(dd, IS_RCVURGENT_START + rcd->ctxt,
12177 IS_RCVURGENT_START + rcd->ctxt, false);
12206 (u64)rcd->rcvavail_timeout <<
14804 int hfi1_set_ctxt_jkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd,
14810 if (!rcd || !rcd->sc)
14813 hw_ctxt = rcd->sc->hw_context;
14818 if (HFI1_CAP_KGET_MASK(rcd->flags, ALLOW_PERM_JKEY))
14834 write_kctxt_csr(dd, rcd->ctxt, RCV_KEY_CTRL, reg);
14839 int hfi1_clear_ctxt_jkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd)
14844 if (!rcd || !rcd->sc)
14847 hw_ctxt = rcd->sc->hw_context;
14860 write_kctxt_csr(dd, rcd->ctxt, RCV_KEY_CTRL, 0);
14865 int hfi1_set_ctxt_pkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd,
14871 if (!rcd || !rcd->sc)
14874 hw_ctxt = rcd->sc->hw_context;