Lines Matching defs:ctxt
5265 u32 is = IS_RCVURGENT_START + rcd->ctxt;
8432 tail = (u32)read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_TAIL);
8522 WARN_ONCE(1, "Napi IRQ handler without napi set up ctxt=%d\n",
8523 rcd->ctxt);
11878 write_kctxt_csr(dd, rcd->ctxt, RCV_AVAIL_TIME_OUT,
11888 u32 ctxt = rcd->ctxt;
11899 write_uctxt_csr(dd, ctxt, RCV_EGR_INDEX_HEAD, reg);
11904 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, reg);
11911 head = (read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_HEAD)
11917 tail = read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_TAIL);
12009 * @ctxt: the context
12013 void set_hdrq_regs(struct hfi1_devdata *dd, u8 ctxt, u8 entsize, u16 hdrcnt)
12019 write_kctxt_csr(dd, ctxt, RCV_HDR_CNT, reg);
12023 write_kctxt_csr(dd, ctxt, RCV_HDR_ENT_SIZE, reg);
12026 write_kctxt_csr(dd, ctxt, RCV_HDR_SIZE, reg);
12032 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
12041 u16 ctxt;
12046 ctxt = rcd->ctxt;
12048 hfi1_cdbg(RCVCTRL, "ctxt %d op 0x%x", ctxt, op);
12050 rcvctrl = read_kctxt_csr(dd, ctxt, RCV_CTXT_CTRL);
12055 write_kctxt_csr(dd, ctxt, RCV_HDR_ADDR,
12058 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
12086 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0);
12090 write_uctxt_csr(dd, ctxt, RCV_EGR_INDEX_HEAD, 0);
12099 write_kctxt_csr(dd, ctxt, RCV_EGR_CTRL, reg);
12113 write_kctxt_csr(dd, ctxt, RCV_TID_CTRL, reg);
12114 if (ctxt == HFI1_CTRL_CTXT)
12125 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
12134 set_intr_bits(dd, IS_RCVAVAIL_START + rcd->ctxt,
12135 IS_RCVAVAIL_START + rcd->ctxt, true);
12139 set_intr_bits(dd, IS_RCVAVAIL_START + rcd->ctxt,
12140 IS_RCVAVAIL_START + rcd->ctxt, false);
12173 set_intr_bits(dd, IS_RCVURGENT_START + rcd->ctxt,
12174 IS_RCVURGENT_START + rcd->ctxt, true);
12176 set_intr_bits(dd, IS_RCVURGENT_START + rcd->ctxt,
12177 IS_RCVURGENT_START + rcd->ctxt, false);
12179 hfi1_cdbg(RCVCTRL, "ctxt %d rcvctrl 0x%llx\n", ctxt, rcvctrl);
12180 write_kctxt_csr(dd, ctxt, RCV_CTXT_CTRL, rcvctrl);
12185 reg = read_kctxt_csr(dd, ctxt, RCV_CTXT_STATUS);
12187 dd_dev_info(dd, "ctxt %d status %lld (blocked)\n",
12188 ctxt, reg);
12189 read_uctxt_csr(dd, ctxt, RCV_HDR_HEAD);
12190 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0x10);
12191 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0x00);
12192 read_uctxt_csr(dd, ctxt, RCV_HDR_HEAD);
12193 reg = read_kctxt_csr(dd, ctxt, RCV_CTXT_STATUS);
12194 dd_dev_info(dd, "ctxt %d status %lld (%s blocked)\n",
12195 ctxt, reg, reg == 0 ? "not" : "still");
12205 write_kctxt_csr(dd, ctxt, RCV_AVAIL_TIME_OUT,
12211 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, reg);
12220 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
14233 u64 ctxt = first_ctxt;
14236 reg |= ctxt << (8 * (i % 8));
14237 ctxt++;
14238 if (ctxt > last_ctxt)
14239 ctxt = first_ctxt;
14409 unsigned qpns_per_vl, ctxt, i, qpn, n = 1, m;
14426 for (i = 0, ctxt = FIRST_KERNEL_KCTXT; i < num_vls; i++) {
14429 for (qpn = 0, tctxt = ctxt;
14443 if (tctxt == ctxt + krcvqs[i])
14444 tctxt = ctxt;
14446 ctxt += krcvqs[i];
14587 reg |= (u64)hfi1_netdev_get_ctxt(dd, ctx_id++)->ctxt << (j * 8);
14834 write_kctxt_csr(dd, rcd->ctxt, RCV_KEY_CTRL, reg);
14860 write_kctxt_csr(dd, rcd->ctxt, RCV_KEY_CTRL, 0);
14886 int hfi1_clear_ctxt_pkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *ctxt)
14891 if (!ctxt || !ctxt->sc)
14894 hw_ctxt = ctxt->sc->hw_context;