Lines Matching defs:clear
1109 * "clear down" routine used for all second tier error interrupt register.
1115 u32 clear; /* clear CSR offset */
5723 /* clear down all observed info as quickly as possible after read */
5905 * The maximum number of times the error clear down will loop before
5934 write_kctxt_csr(dd, context, eri->clear, reg);
5981 * clear-down mechanism cannot be used because we cannot clear the
6519 /* clear lcb run: LCB_CFG_RUN.EN = 0 */
6752 static void adjust_rcvctrl(struct hfi1_devdata *dd, u64 add, u64 clear)
6760 rcvctrl &= ~clear;
6770 static inline void clear_rcvctrl(struct hfi1_devdata *dd, u64 clear)
6772 adjust_rcvctrl(dd, 0, clear);
6835 /* waiting until all indicators are clear */
6932 * Unfreeze the hardware - clear the freeze, wait for each
6933 * block's frozen bit to clear, then clear the frozen flag.
7542 /* set (14b only) or clear sideband credit */
8337 /* phase 1: scan and clear all handled interrupts */
8345 /* only clear if anything is set */
8379 /* clear the interrupt(s) */
8394 * Clear the receive interrupt. Use a read of the interrupt clear CSR
8471 * Hold IRQs so we can safely clear the interrupt and
8473 * check and the interrupt clear. If a packet arrived, force another
8601 /* clear current state, set new state */
9390 /* reset our fabric serdes to clear any lingering problems */
10782 /* clear old transient LINKINIT_REASON code */
11395 /* spin until the given per-VL status mask bits clear */
11414 "%s credit change status not clearing after %dms, mask 0x%llx, not clear 0x%llx\n",
13215 * read_mod_write() - Calculate the IRQ register index and set/clear the bits
13218 * @bits: the bits to set or clear
13219 * @set: true == set the bits, false == clear the bits
13241 * @first: first IRQ source to set/clear
13242 * @last: last IRQ source (inclusive) to set/clear
13243 * @set: true == set the bits, false == clear the bits
13309 /* clear from the handled mask of the general interrupt */
13371 /* clear all pending interrupts */
13636 * Use the ctrl_bits in CceCtrl to clear the status_bits in CceStatus.
13649 /* clear the condition */
13652 /* wait for the condition to clear */
13660 "Timeout waiting for CceStatus to clear bits 0x%llx, remaining 0x%llx\n",
13675 /* CCE_CTRL - bits clear automatically */
13676 /* CCE_STATUS read-only, use CceCtrl to clear */
13727 /* init RSA engine to clear lingering errors */
13869 * clear.
13941 /* this is a clear-down */
14093 * DC Reset: do a full DC reset before the register clear.
14096 * across the clear.
14137 /* clear the DC reset */
14679 /* only actually clear the rule if it's the last user asking to do so */