Lines Matching defs:bits
189 /* We use 8 most significant Soure QPN bits as entropy fpr AIP */
277 /* all CceStatus sub-block freeze bits */
282 /* all CceStatus sub-block TXE pause bits */
286 /* all CceStatus sub-block RXE pause bits */
564 /* SendEgressErrInfo bits that correspond to a PortXmitDiscard counter */
1739 /* Software counters for the error status bits within MISC_ERR_STATUS */
1872 * error status bits within CceErrStatus
2244 * error status bits within RcvErrStatus
2824 * error status bits within SendPioErrStatus
3152 * error status bits within SendDmaErrStatus
3192 * error status bits within SendEgressErrStatus
3772 * error status bits within SendErrStatus
3803 * error status bits within SendCtxtErrStatus
3852 * error status bits within SendDmaEngErrStatus
5340 /* any undocumented bits left? */
5342 snprintf(extra, sizeof(extra), "bits 0x%llx", flags);
5735 * Count all applicable bits as individual errors and
5746 * The driver is attributing all bits in the info register
5747 * to the packet that triggered this call, but bits
5752 * multiple bits set in the info register are due to a
5919 * and can't be fixed, so mask the error bits.
5941 dd_dev_err(dd, "Repeating %s bits 0x%llx - masking\n",
5944 * Read-modify-write so any other masked bits
5982 * error bits until several other long-running items are done first.
6035 * Update the counters for the corresponding status bits.
6062 * Update the counters for the corresponding status bits.
6842 "Time out waiting for SPC %sfreeze, bits 0x%llx, expecting 0x%llx, continuing",
7404 * + bits [7:4] contain the number of active transmitters
7405 * + bits [3:0] contain the number of active receivers
7451 /* cache the active egress rate (units {10^6 bits/sec]) */
8387 dd_dev_info_ratelimited(dd, "SDMA engine %u interrupt, but no status bits set\n",
8852 /* top 16 bits are in a different register */
9354 * Translate from the OPA_LINK_WIDTH handed to us by the FM to bits
11044 * "fill in with your supported value" have all the bits in the
11261 /* each register contains 16 SC->VLnt mappings, 4 bits each */
11395 /* spin until the given per-VL status mask bits clear */
11505 * NOTE: Assumes that the individual VL bits are adjacent and in
12547 * the number of flits sent/recv. If the total flits exceeds 32bits then
12727 /* Counter is 32 bits */
12742 /* Counter is 32 bits */
12754 /* Counter is 32 bits */
12829 /* Counter is 32 bits */
12842 /* Counter is 32 bits */
13215 * read_mod_write() - Calculate the IRQ register index and set/clear the bits
13218 * @bits: the bits to set or clear
13219 * @set: true == set the bits, false == clear the bits
13222 static void read_mod_write(struct hfi1_devdata *dd, u16 src, u64 bits,
13231 reg |= bits;
13233 reg &= ~bits;
13243 * @set: true == set the bits, false == clear the bits
13249 u64 bits = 0;
13262 if (!bit && bits) {
13263 read_mod_write(dd, src - 1, bits, set);
13264 bits = 0;
13266 bits |= BIT_ULL(bit);
13268 read_mod_write(dd, last, bits, set);
13591 * written before reading to set the ECC/parity bits.
13660 "Timeout waiting for CceStatus to clear bits 0x%llx, remaining 0x%llx\n",
13675 /* CCE_CTRL - bits clear automatically */
14362 /* determine bits for qpn */
14370 /* determine bits for vl */
14403 * The number of vl bits (n) and the number of qpn bits (m) are computed to
14506 * There are only enough bits in offset for the table size, so
15008 /* Clear all interrupt status bits */
15014 /* Set all interrupt status bits */
15137 /* the variable size will remove unwanted bits */
15373 /* rates here are in units of 10^6 bits/sec */