Lines Matching refs:aenq
197 struct efa_com_aenq *aenq = &edev->aenq;
203 ibdev_err(edev->efa_dev, "aenq handlers pointer is NULL\n");
207 size = EFA_ASYNC_QUEUE_DEPTH * sizeof(*aenq->entries);
208 aenq->entries = dma_alloc_coherent(edev->dmadev, size, &aenq->dma_addr,
210 if (!aenq->entries)
213 aenq->aenq_handlers = aenq_handlers;
214 aenq->depth = EFA_ASYNC_QUEUE_DEPTH;
215 aenq->cc = 0;
216 aenq->phase = 1;
218 addr_low = EFA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr);
219 addr_high = EFA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr);
224 EFA_SET(&aenq_caps, EFA_REGS_AENQ_CAPS_AENQ_DEPTH, aenq->depth);
228 aenq->msix_vector_idx);
235 writel(edev->aenq.cc, edev->reg_bar + EFA_REGS_AENQ_CONS_DB_OFF);
661 struct efa_com_aenq *aenq = &edev->aenq;
677 size = aenq->depth * sizeof(*aenq->entries);
678 dma_free_coherent(edev->dmadev, size, aenq->entries, aenq->dma_addr);
816 struct efa_aenq_handlers *aenq_handlers = edev->aenq.aenq_handlers;
829 * Go over the async event notification queue and call the proper aenq handler.
834 struct efa_com_aenq *aenq = &edev->aenq;
841 ci = aenq->cc & (aenq->depth - 1);
842 phase = aenq->phase;
843 aenq_e = &aenq->entries[ci]; /* Get first entry */
864 if (ci == aenq->depth) {
868 aenq_e = &aenq->entries[ci];
872 aenq->cc += processed;
873 aenq->phase = phase;
875 /* Don't update aenq doorbell if there weren't any processed events */
880 writel(aenq->cc, edev->reg_bar + EFA_REGS_AENQ_CONS_DB_OFF);