Lines Matching refs:ADF4371_REG
21 #define ADF4371_REG(x) (x)
109 [ADF4371_CH_RF8] = { ADF4371_REG(0x25), 2 },
110 [ADF4371_CH_RFAUX8] = { ADF4371_REG(0x72), 3 },
111 [ADF4371_CH_RF16] = { ADF4371_REG(0x25), 3 },
112 [ADF4371_CH_RF32] = { ADF4371_REG(0x25), 4 },
116 { ADF4371_REG(0x0), 0x18 },
117 { ADF4371_REG(0x12), 0x40 },
118 { ADF4371_REG(0x1E), 0x48 },
119 { ADF4371_REG(0x20), 0x14 },
120 { ADF4371_REG(0x22), 0x00 },
121 { ADF4371_REG(0x23), 0x00 },
122 { ADF4371_REG(0x24), 0x80 },
123 { ADF4371_REG(0x25), 0x07 },
124 { ADF4371_REG(0x27), 0xC5 },
125 { ADF4371_REG(0x28), 0x83 },
126 { ADF4371_REG(0x2C), 0x44 },
127 { ADF4371_REG(0x2D), 0x11 },
128 { ADF4371_REG(0x2E), 0x12 },
129 { ADF4371_REG(0x2F), 0x94 },
130 { ADF4371_REG(0x32), 0x04 },
131 { ADF4371_REG(0x35), 0xFA },
132 { ADF4371_REG(0x36), 0x30 },
133 { ADF4371_REG(0x39), 0x07 },
134 { ADF4371_REG(0x3A), 0x55 },
135 { ADF4371_REG(0x3E), 0x0C },
136 { ADF4371_REG(0x3F), 0x80 },
137 { ADF4371_REG(0x40), 0x50 },
138 { ADF4371_REG(0x41), 0x28 },
139 { ADF4371_REG(0x47), 0xC0 },
140 { ADF4371_REG(0x52), 0xF4 },
141 { ADF4371_REG(0x70), 0x03 },
142 { ADF4371_REG(0x71), 0x60 },
143 { ADF4371_REG(0x72), 0x32 },
288 ret = regmap_bulk_write(st->regmap, ADF4371_REG(0x11), st->buf, 10);
295 ret = regmap_write(st->regmap, ADF4371_REG(0x1F), st->ref_div_factor);
299 ret = regmap_update_bits(st->regmap, ADF4371_REG(0x24),
307 ret = regmap_write(st->regmap, ADF4371_REG(0x26), cp_bleed);
317 ret = regmap_write(st->regmap, ADF4371_REG(0x2B), int_mode);
321 return regmap_write(st->regmap, ADF4371_REG(0x10), st->integer & 0xFF);
337 ret = regmap_read(st->regmap, ADF4371_REG(0x7C), &readval);
482 ret = regmap_write(st->regmap, ADF4371_REG(0x0), ADF4371_RESET_CMD);
493 ret = regmap_update_bits(st->regmap, ADF4371_REG(0x25),
501 ret = regmap_update_bits(st->regmap, ADF4371_REG(0x0),
540 return regmap_bulk_write(st->regmap, ADF4371_REG(0x30), st->buf, 5);