Lines Matching refs:ret
170 #define AD9523_CLK_DIST_DIV_PHASE_REV(x) ((ret >> 18) & 0x3F)
172 #define AD9523_CLK_DIST_DIV_REV(x) (((ret >> 8) & 0x3FF) + 1)
302 int ret;
323 ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
324 if (ret < 0)
325 dev_err(&indio_dev->dev, "read failed (%d)", ret);
327 ret = be32_to_cpu(st->data[1].d32) & (0xFFFFFF >>
330 return ret;
337 int ret;
353 ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
355 if (ret < 0)
356 dev_err(&indio_dev->dev, "write failed (%d)", ret);
358 return ret;
370 int ret;
375 ret = ad9523_read(indio_dev, AD9523_PLL1_OUTPUT_CHANNEL_CTRL);
376 if (ret < 0)
380 ret |= mask;
383 ret &= ~mask;
385 ret = ad9523_write(indio_dev,
386 AD9523_PLL1_OUTPUT_CHANNEL_CTRL, ret);
389 ret = ad9523_read(indio_dev, AD9523_PLL1_OUTPUT_CTRL);
390 if (ret < 0)
394 ret |= mask;
396 ret &= ~mask;
397 ret = ad9523_write(indio_dev, AD9523_PLL1_OUTPUT_CTRL, ret);
400 ret = ad9523_read(indio_dev, AD9523_PLL1_OUTPUT_CHANNEL_CTRL);
401 if (ret < 0)
405 ret |= mask;
407 ret &= ~mask;
408 ret = ad9523_write(indio_dev,
409 AD9523_PLL1_OUTPUT_CHANNEL_CTRL, ret);
417 return ret;
448 int ret, tmp;
450 ret = ad9523_write(indio_dev, AD9523_EEPROM_CTRL1,
452 if (ret < 0)
453 return ret;
454 ret = ad9523_write(indio_dev, AD9523_EEPROM_CTRL2,
456 if (ret < 0)
457 return ret;
462 ret = ad9523_read(indio_dev,
464 if (ret < 0)
465 return ret;
466 } while ((ret & AD9523_EEPROM_DATA_XFER_IN_PROGRESS) && tmp--);
468 ret = ad9523_write(indio_dev, AD9523_EEPROM_CTRL1, 0);
469 if (ret < 0)
470 return ret;
472 ret = ad9523_read(indio_dev, AD9523_EEPROM_ERROR_READBACK);
473 if (ret < 0)
474 return ret;
476 if (ret & AD9523_EEPROM_ERROR_READBACK_FAIL) {
478 ret = -EIO;
481 return ret;
486 int ret, tmp;
488 ret = ad9523_read(indio_dev, AD9523_STATUS_SIGNALS);
489 if (ret < 0)
490 return ret;
492 tmp = ret;
495 ret = ad9523_write(indio_dev, AD9523_STATUS_SIGNALS, tmp);
496 if (ret < 0)
497 return ret;
502 ret = ad9523_write(indio_dev, AD9523_STATUS_SIGNALS, tmp);
503 if (ret < 0)
504 return ret;
517 int ret;
519 ret = strtobool(buf, &state);
520 if (ret < 0)
521 return ret;
529 ret = ad9523_sync(indio_dev);
532 ret = ad9523_store_eeprom(indio_dev);
535 ret = -ENODEV;
539 return ret ? ret : len;
549 int ret;
552 ret = ad9523_read(indio_dev, AD9523_READBACK_0);
553 if (ret >= 0) {
554 ret = sprintf(buf, "%d\n", !!(ret & (1 <<
559 return ret;
638 int ret;
641 ret = ad9523_read(indio_dev, AD9523_CHANNEL_CLOCK_DIST(chan->channel));
644 if (ret < 0)
645 return ret;
649 *val = !(ret & AD9523_CLK_DIST_PWR_DOWN_EN);
653 AD9523_CLK_DIST_DIV_REV(ret);
656 code = (AD9523_CLK_DIST_DIV_PHASE_REV(ret) * 3141592) /
657 AD9523_CLK_DIST_DIV_REV(ret);
674 int ret, tmp, code;
677 ret = ad9523_read(indio_dev, AD9523_CHANNEL_CLOCK_DIST(chan->channel));
678 if (ret < 0)
681 reg = ret;
692 ret = -EINVAL;
695 ret = ad9523_set_clock_provider(indio_dev, chan->channel, val);
696 if (ret < 0)
705 tmp = (code * AD9523_CLK_DIST_DIV_REV(ret)) / 3141592;
711 ret = -EINVAL;
715 ret = ad9523_write(indio_dev, AD9523_CHANNEL_CLOCK_DIST(chan->channel),
717 if (ret < 0)
723 return ret;
731 int ret;
735 ret = ad9523_write(indio_dev, reg | AD9523_R1B, writeval);
738 ret = ad9523_read(indio_dev, reg | AD9523_R1B);
739 if (ret < 0)
741 *readval = ret;
742 ret = 0;
748 return ret;
764 int ret, i;
766 ret = ad9523_write(indio_dev, AD9523_SERIAL_PORT_CONFIG,
770 if (ret < 0)
771 return ret;
773 ret = ad9523_write(indio_dev, AD9523_READBACK_CTRL,
775 if (ret < 0)
776 return ret;
778 ret = ad9523_io_update(indio_dev);
779 if (ret < 0)
780 return ret;
785 ret = ad9523_write(indio_dev, AD9523_PLL1_REF_A_DIVIDER,
787 if (ret < 0)
788 return ret;
790 ret = ad9523_write(indio_dev, AD9523_PLL1_REF_B_DIVIDER,
792 if (ret < 0)
793 return ret;
795 ret = ad9523_write(indio_dev, AD9523_PLL1_FEEDBACK_DIVIDER,
797 if (ret < 0)
798 return ret;
800 ret = ad9523_write(indio_dev, AD9523_PLL1_CHARGE_PUMP_CTRL,
805 if (ret < 0)
806 return ret;
808 ret = ad9523_write(indio_dev, AD9523_PLL1_INPUT_RECEIVERS_CTRL,
816 if (ret < 0)
817 return ret;
819 ret = ad9523_write(indio_dev, AD9523_PLL1_REF_CTRL,
828 if (ret < 0)
829 return ret;
831 ret = ad9523_write(indio_dev, AD9523_PLL1_MISC_CTRL,
834 if (ret < 0)
835 return ret;
837 ret = ad9523_write(indio_dev, AD9523_PLL1_LOOP_FILTER_CTRL,
839 if (ret < 0)
840 return ret;
845 ret = ad9523_write(indio_dev, AD9523_PLL2_CHARGE_PUMP,
848 if (ret < 0)
849 return ret;
851 ret = ad9523_write(indio_dev, AD9523_PLL2_FEEDBACK_DIVIDER_AB,
854 if (ret < 0)
855 return ret;
857 ret = ad9523_write(indio_dev, AD9523_PLL2_CTRL,
861 if (ret < 0)
862 return ret;
870 ret = ad9523_write(indio_dev, AD9523_PLL2_VCO_CTRL,
872 if (ret < 0)
873 return ret;
875 ret = ad9523_write(indio_dev, AD9523_PLL2_VCO_DIVIDER,
882 if (ret < 0)
883 return ret;
895 ret = ad9523_write(indio_dev, AD9523_PLL2_R2_DIVIDER,
897 if (ret < 0)
898 return ret;
900 ret = ad9523_write(indio_dev, AD9523_PLL2_LOOP_FILTER_CTRL,
906 if (ret < 0)
907 return ret;
913 ret = ad9523_write(indio_dev,
926 if (ret < 0)
927 return ret;
929 ret = ad9523_vco_out_map(indio_dev, chan->channel_num,
931 if (ret < 0)
932 return ret;
948 ret = ad9523_write(indio_dev,
952 if (ret < 0)
953 return ret;
956 ret = ad9523_write(indio_dev, AD9523_POWER_DOWN_CTRL, 0);
957 if (ret < 0)
958 return ret;
960 ret = ad9523_write(indio_dev, AD9523_STATUS_SIGNALS,
962 if (ret < 0)
963 return ret;
965 ret = ad9523_io_update(indio_dev);
966 if (ret < 0)
967 return ret;
984 int ret;
1001 ret = regulator_enable(st->reg);
1002 if (ret)
1003 return ret;
1005 ret = devm_add_action_or_reset(&spi->dev, ad9523_reg_disable,
1007 if (ret)
1008 return ret;
1042 ret = ad9523_setup(indio_dev);
1043 if (ret < 0)
1044 return ret;