Lines Matching refs:dma
34 #include <linux/dma-mapping.h>
51 struct tiadc_dma dma;
237 struct tiadc_dma *dma = &adc_dev->dma;
241 data = dma->buf + dma->current_period * dma->period_size;
242 dma->current_period = 1 - dma->current_period; /* swap the buffer ID */
244 for (i = 0; i < dma->period_size; i += indio_dev->scan_bytes) {
253 struct tiadc_dma *dma = &adc_dev->dma;
256 dma->current_period = 0; /* We start to fill period 0 */
264 dma->fifo_thresh = rounddown(FIFO1_THRESHOLD + 1,
267 dma->period_size = rounddown(DMA_BUFFER_SIZE / 2,
268 (dma->fifo_thresh + 1) * sizeof(u16));
270 dma->conf.src_maxburst = dma->fifo_thresh + 1;
271 dmaengine_slave_config(dma->chan, &dma->conf);
273 desc = dmaengine_prep_dma_cyclic(dma->chan, dma->addr,
274 dma->period_size * 2,
275 dma->period_size, DMA_DEV_TO_MEM,
283 dma->cookie = dmaengine_submit(desc);
285 dma_async_issue_pending(dma->chan);
287 tiadc_writel(adc_dev, REG_FIFO1THR, dma->fifo_thresh);
288 tiadc_writel(adc_dev, REG_DMA1REQ, dma->fifo_thresh);
314 struct tiadc_dma *dma = &adc_dev->dma;
326 if (dma->chan)
335 if (!dma->chan)
345 struct tiadc_dma *dma = &adc_dev->dma;
353 if (dma->chan) {
355 dmaengine_terminate_async(dma->chan);
529 struct tiadc_dma *dma = &adc_dev->dma;
533 dma->conf.direction = DMA_DEV_TO_MEM;
534 dma->conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
535 dma->conf.src_addr = adc_dev->mfd_tscadc->tscadc_phys_base + REG_FIFO1;
541 dma->chan = dma_request_chan(adc_dev->mfd_tscadc->dev, "fifo1");
542 if (IS_ERR(dma->chan)) {
543 int ret = PTR_ERR(dma->chan);
545 dma->chan = NULL;
550 dma->buf = dma_alloc_coherent(dma->chan->device->dev, DMA_BUFFER_SIZE,
551 &dma->addr, GFP_KERNEL);
552 if (!dma->buf)
557 dma_release_channel(dma->chan);
661 struct tiadc_dma *dma = &adc_dev->dma;
664 if (dma->chan) {
665 dma_free_coherent(dma->chan->device->dev, DMA_BUFFER_SIZE,
666 dma->buf, dma->addr);
667 dma_release_channel(dma->chan);