Lines Matching defs:adc
11 #include <linux/iio/adc/stm32-dfsdm-adc.h>
315 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
316 struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id];
336 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
337 struct regmap *regmap = adc->dfsdm->regmap;
342 for_each_set_bit(bit, &adc->smask, sizeof(adc->smask) * BITS_PER_BYTE) {
356 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
357 struct regmap *regmap = adc->dfsdm->regmap;
361 for_each_set_bit(bit, &adc->smask, sizeof(adc->smask) * BITS_PER_BYTE) {
391 static int stm32_dfsdm_start_filter(struct stm32_dfsdm_adc *adc,
395 struct stm32_dfsdm *dfsdm = adc->dfsdm;
405 if (adc->nconv > 1 || trig)
426 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
427 struct regmap *regmap = adc->dfsdm->regmap;
455 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
456 struct regmap *regmap = adc->dfsdm->regmap;
457 struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[fl_id];
469 if (adc->nconv == 1 && !trig &&
483 for_each_set_bit(bit, &adc->smask,
484 sizeof(adc->smask) * BITS_PER_BYTE) {
502 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
503 struct regmap *regmap = adc->dfsdm->regmap;
504 struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[fl_id];
557 if (adc->nconv == 1 && !trig) {
558 bit = __ffs(adc->smask);
571 for_each_set_bit(bit, &adc->smask,
572 sizeof(adc->smask) * BITS_PER_BYTE) {
581 cr1 = DFSDM_CR1_JSCAN((adc->nconv > 1) ? 1 : 0);
608 "st,adc-channels", chan_idx,
612 " Error parsing 'st,adc-channels' for idx %d\n",
624 "st,adc-channel-names", chan_idx,
628 " Error parsing 'st,adc-channel-names' for idx %d\n",
637 "st,adc-channel-types", chan_idx,
649 "st,adc-channel-clk-src", chan_idx,
661 "st,adc-alt-channel", chan_idx,
674 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
676 return snprintf(buf, PAGE_SIZE, "%d\n", adc->spi_freq);
683 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
697 adc->sample_freq = spi_freq / oversamp;
698 adc->oversamp = oversamp;
708 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
709 struct stm32_dfsdm_channel *ch = &adc->dfsdm->ch_list[chan->channel];
710 unsigned int sample_freq = adc->sample_freq;
731 adc->spi_freq = spi_freq;
739 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
740 struct regmap *regmap = adc->dfsdm->regmap;
743 ret = stm32_dfsdm_channels_configure(indio_dev, adc->fl_id, trig);
751 ret = stm32_dfsdm_filter_configure(indio_dev, adc->fl_id, trig);
755 ret = stm32_dfsdm_start_filter(adc, adc->fl_id, trig);
762 regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
772 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
773 struct regmap *regmap = adc->dfsdm->regmap;
775 stm32_dfsdm_stop_filter(adc->dfsdm, adc->fl_id);
777 regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
786 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
797 adc->buf_sz = min(rx_buf_sz, watermark * 2 * adc->nconv);
802 static unsigned int stm32_dfsdm_adc_dma_residue(struct stm32_dfsdm_adc *adc)
807 status = dmaengine_tx_status(adc->dma_chan,
808 adc->dma_chan->cookie,
812 unsigned int i = adc->buf_sz - state.residue;
816 if (i >= adc->bufi)
817 size = i - adc->bufi;
819 size = adc->buf_sz + i - adc->bufi;
827 static inline void stm32_dfsdm_process_data(struct stm32_dfsdm_adc *adc,
830 struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id];
832 unsigned int i = adc->nconv;
854 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
855 int available = stm32_dfsdm_adc_dma_residue(adc);
868 adc->bufi, available);
869 old_pos = adc->bufi;
872 s32 *buffer = (s32 *)&adc->rx_buf[adc->bufi];
874 stm32_dfsdm_process_data(adc, buffer);
877 adc->bufi += indio_dev->scan_bytes;
878 if (adc->bufi >= adc->buf_sz) {
879 if (adc->cb)
880 adc->cb(&adc->rx_buf[old_pos],
881 adc->buf_sz - old_pos, adc->cb_priv);
882 adc->bufi = 0;
894 if (adc->dev_data->type == DFSDM_IIO)
897 if (adc->cb)
898 adc->cb(&adc->rx_buf[old_pos], adc->bufi - old_pos,
899 adc->cb_priv);
904 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
911 .src_addr = (dma_addr_t)adc->dfsdm->phys_base,
918 if (!adc->dma_chan)
922 adc->buf_sz, adc->buf_sz / 2);
924 if (adc->nconv == 1 && !indio_dev->trig)
925 config.src_addr += DFSDM_RDATAR(adc->fl_id);
927 config.src_addr += DFSDM_JDATAR(adc->fl_id);
928 ret = dmaengine_slave_config(adc->dma_chan, &config);
933 desc = dmaengine_prep_dma_cyclic(adc->dma_chan,
934 adc->dma_buf,
935 adc->buf_sz, adc->buf_sz / 2,
950 dma_async_issue_pending(adc->dma_chan);
952 if (adc->nconv == 1 && !indio_dev->trig) {
954 ret = regmap_update_bits(adc->dfsdm->regmap,
955 DFSDM_CR1(adc->fl_id),
960 ret = regmap_update_bits(adc->dfsdm->regmap,
961 DFSDM_CR1(adc->fl_id),
972 dmaengine_terminate_all(adc->dma_chan);
979 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
981 if (!adc->dma_chan)
984 regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR1(adc->fl_id),
986 dmaengine_terminate_all(adc->dma_chan);
992 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
994 adc->nconv = bitmap_weight(scan_mask, indio_dev->masklength);
995 adc->smask = *scan_mask;
997 dev_dbg(&indio_dev->dev, "nconv=%d mask=%lx\n", adc->nconv, *scan_mask);
1004 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1007 /* Reset adc buffer index */
1008 adc->bufi = 0;
1010 if (adc->hwc) {
1011 ret = iio_hw_consumer_enable(adc->hwc);
1016 ret = stm32_dfsdm_start_dfsdm(adc->dfsdm);
1037 stm32_dfsdm_stop_dfsdm(adc->dfsdm);
1039 if (adc->hwc)
1040 iio_hw_consumer_disable(adc->hwc);
1047 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1053 stm32_dfsdm_stop_dfsdm(adc->dfsdm);
1055 if (adc->hwc)
1056 iio_hw_consumer_disable(adc->hwc);
1082 struct stm32_dfsdm_adc *adc;
1086 adc = iio_priv(iio_dev);
1088 adc->cb = cb;
1089 adc->cb_priv = private;
1102 struct stm32_dfsdm_adc *adc;
1106 adc = iio_priv(iio_dev);
1108 adc->cb = NULL;
1109 adc->cb_priv = NULL;
1118 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1122 reinit_completion(&adc->completion);
1124 adc->buffer = res;
1126 ret = stm32_dfsdm_start_dfsdm(adc->dfsdm);
1130 ret = regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
1135 adc->nconv = 1;
1136 adc->smask = BIT(chan->scan_index);
1139 regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
1144 timeout = wait_for_completion_interruptible_timeout(&adc->completion,
1148 regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
1160 stm32_dfsdm_process_data(adc, res);
1163 stm32_dfsdm_stop_dfsdm(adc->dfsdm);
1172 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1173 struct stm32_dfsdm_channel *ch = &adc->dfsdm->ch_list[chan->channel];
1179 spi_freq = adc->dfsdm->spi_master_freq;
1183 spi_freq = adc->dfsdm->spi_master_freq / 2;
1186 spi_freq = adc->spi_freq;
1199 adc->sample_freq, spi_freq / val);
1200 adc->oversamp = val;
1201 adc->sample_freq = spi_freq / val;
1226 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1234 ret = iio_hw_consumer_enable(adc->hwc);
1243 iio_hw_consumer_disable(adc->hwc);
1255 *val = adc->oversamp;
1260 *val = adc->sample_freq;
1292 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1293 struct regmap *regmap = adc->dfsdm->regmap;
1296 regmap_read(regmap, DFSDM_ISR(adc->fl_id), &status);
1297 regmap_read(regmap, DFSDM_CR2(adc->fl_id), &int_en);
1301 regmap_read(regmap, DFSDM_RDATAR(adc->fl_id), adc->buffer);
1302 complete(&adc->completion);
1308 regmap_update_bits(regmap, DFSDM_ICR(adc->fl_id),
1333 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1335 if (adc->dma_chan) {
1336 dma_free_coherent(adc->dma_chan->device->dev,
1338 adc->rx_buf, adc->dma_buf);
1339 dma_release_channel(adc->dma_chan);
1346 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1348 adc->dma_chan = dma_request_chan(dev, "rx");
1349 if (IS_ERR(adc->dma_chan)) {
1350 int ret = PTR_ERR(adc->dma_chan);
1352 adc->dma_chan = NULL;
1356 adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev,
1358 &adc->dma_buf, GFP_KERNEL);
1359 if (!adc->rx_buf) {
1360 dma_release_channel(adc->dma_chan);
1373 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1376 ret = stm32_dfsdm_channel_parse_of(adc->dfsdm, indio_dev, ch);
1391 if (adc->dev_data->type == DFSDM_AUDIO) {
1400 return stm32_dfsdm_chan_configure(adc->dfsdm,
1401 &adc->dfsdm->ch_list[ch->channel]);
1407 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1424 d_ch = &adc->dfsdm->ch_list[ch->channel];
1426 adc->spi_freq = adc->dfsdm->spi_master_freq;
1437 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1441 adc->oversamp = DFSDM_DEFAULT_OVERSAMPLING;
1442 ret = stm32_dfsdm_compute_all_osrs(indio_dev, adc->oversamp);
1447 "st,adc-channels");
1448 if (num_ch < 0 || num_ch > adc->dfsdm->num_chs) {
1449 dev_err(&indio_dev->dev, "Bad st,adc-channels\n");
1454 adc->hwc = devm_iio_hw_consumer_alloc(&indio_dev->dev);
1455 if (IS_ERR(adc->hwc))
1475 init_completion(&adc->completion);
1515 .compatible = "st,stm32-dfsdm-adc",
1529 struct stm32_dfsdm_adc *adc;
1537 iio = devm_iio_device_alloc(dev, sizeof(*adc));
1543 adc = iio_priv(iio);
1544 adc->dfsdm = dev_get_drvdata(dev->parent);
1551 ret = of_property_read_u32(dev->of_node, "reg", &adc->fl_id);
1552 if (ret != 0 || adc->fl_id >= adc->dfsdm->num_fls) {
1562 snprintf(name, sizeof("dfsdm-pdm0"), "dfsdm-pdm%d", adc->fl_id);
1565 snprintf(name, sizeof("dfsdm-adc0"), "dfsdm-adc%d", adc->fl_id);
1590 adc->dfsdm->fl_list[adc->fl_id].ford = val;
1594 adc->dfsdm->fl_list[adc->fl_id].sync_mode = val;
1596 adc->dev_data = dev_data;
1626 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1628 if (adc->dev_data->type == DFSDM_AUDIO)
1649 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1657 ch = &adc->dfsdm->ch_list[chan->channel];
1658 ret = stm32_dfsdm_chan_configure(adc->dfsdm, ch);
1674 .name = "stm32-dfsdm-adc",