Lines Matching refs:smpr
127 * @smpr: smpr1 & smpr2 registers offset array
140 const u32 smpr[2];
315 /* STM32F4_ADC_SMPR2: smpr[] index, mask, shift for SMP0 to SMP9 */
326 /* STM32F4_ADC_SMPR1, smpr[] index, mask, shift for SMP10 to SMP18 */
354 .smpr = { STM32F4_ADC_SMPR1, STM32F4_ADC_SMPR2 },
408 /* STM32H7_ADC_SMPR1, smpr[] index, mask, shift for SMP0 to SMP9 */
419 /* STM32H7_ADC_SMPR2, smpr[] index, mask, shift for SMP10 to SMP19 */
448 .smpr = { STM32H7_ADC_SMPR1, STM32H7_ADC_SMPR2 },
1008 stm32_adc_writel(adc, adc->cfg->regs->smpr[0], adc->smpr_val[0]);
1009 stm32_adc_writel(adc, adc->cfg->regs->smpr[1], adc->smpr_val[1]);
1173 stm32_adc_writel(adc, regs->smpr[0], adc->smpr_val[0]);
1174 stm32_adc_writel(adc, regs->smpr[1], adc->smpr_val[1]);
1676 const struct stm32_adc_regs *smpr = &adc->cfg->regs->smp_bits[channel];
1677 u32 period_ns, shift = smpr->shift, mask = smpr->mask;
1678 unsigned int smp, r = smpr->reg;