Lines Matching defs:offset
92 * @calfact_s: Calibration offset for single ended channels
93 * @calfact_d: Calibration offset in differential
106 * @reg: register offset
118 * @dr: data register offset
127 * @smpr: smpr1 & smpr2 registers offset array
177 * @offset: ADC instance register offset in ADC block
200 u32 offset;
455 * @reg: reg offset in adc instance
457 * Note: All instances share same base, with 0x0, 0x100 or 0x200 offset resp.
462 return readl_relaxed(adc->common->base + adc->offset + reg);
473 return readw_relaxed(adc->common->base + adc->offset + reg);
478 writel_relaxed(val, adc->common->base + adc->offset + reg);
787 /* Read offset calibration */
865 * - 20 ADC clock cycle for the offset calibration
907 * will run simultaneously with offset calibration.
1392 * @reg: register offset
1397 * echo [ADC reg offset] > direct_reg_access
1862 config.src_addr += adc->offset + adc->cfg->regs->dr;
1909 ret = of_property_read_u32(pdev->dev.of_node, "reg", &adc->offset);