Lines Matching defs:channel
38 #define STM32_ADC_CH_SZ 10 /* max channel name size */
188 * @dma_chan: dma channel
192 * @difsel: bitmask to set single-ended/differential channel
196 * @chan_name: channel name array
312 * Sorted so it can be indexed by channel number.
405 * Sorted so it can be indexed by channel number.
1014 * Assign one channel per SQ entry in regular
1022 __func__, chan->channel, i);
1026 val |= chan->channel << sqr[i].shift;
1142 * @chan: IIO channel
1145 * The function performs a single conversion on a given channel:
1147 * - Program sequencer with one channel (e.g. in SQ1 with len = 1)
1179 val |= chan->channel << regs->sqr[1].shift;
1295 * channel may be read. Unconditionally disable interrupts
1383 if (indio_dev->channels[i].channel == iiospec->args[0])
1674 static void stm32_adc_smpr_init(struct stm32_adc *adc, int channel, u32 smp_ns)
1676 const struct stm32_adc_regs *smpr = &adc->cfg->regs->smp_bits[channel];
1700 chan->channel = vinp;
1720 adc->pcsel |= BIT(chan->channel);
1723 adc->difsel |= BIT(chan->channel);
1784 dev_err(&indio_dev->dev, "Invalid channel %d\n", val);
1792 "channel %d miss-configured\n", val);
1804 dev_err(&indio_dev->dev, "Invalid channel in%d-in%d\n",
1819 * value per channel.
1824 stm32_adc_smpr_init(adc, channels[i].channel, smp);
1844 "DMA channel request failed with\n");
1859 /* Configure DMA channel to read data register */