Lines Matching defs:adc
29 #include "stm32-adc-core.h"
91 * struct stm32_adc_calib - optional adc calibration data
181 * @clk: clock for this adc instance
182 * @irq: interrupt for this adc instance
454 * @adc: stm32 adc instance
455 * @reg: reg offset in adc instance
460 static u32 stm32_adc_readl(struct stm32_adc *adc, u32 reg)
462 return readl_relaxed(adc->common->base + adc->offset + reg);
465 #define stm32_adc_readl_addr(addr) stm32_adc_readl(adc, addr)
471 static u16 stm32_adc_readw(struct stm32_adc *adc, u32 reg)
473 return readw_relaxed(adc->common->base + adc->offset + reg);
476 static void stm32_adc_writel(struct stm32_adc *adc, u32 reg, u32 val)
478 writel_relaxed(val, adc->common->base + adc->offset + reg);
481 static void stm32_adc_set_bits(struct stm32_adc *adc, u32 reg, u32 bits)
485 spin_lock_irqsave(&adc->lock, flags);
486 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) | bits);
487 spin_unlock_irqrestore(&adc->lock, flags);
490 static void stm32_adc_clr_bits(struct stm32_adc *adc, u32 reg, u32 bits)
494 spin_lock_irqsave(&adc->lock, flags);
495 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) & ~bits);
496 spin_unlock_irqrestore(&adc->lock, flags);
501 * @adc: stm32 adc instance
503 static void stm32_adc_conv_irq_enable(struct stm32_adc *adc)
505 stm32_adc_set_bits(adc, adc->cfg->regs->ier_eoc.reg,
506 adc->cfg->regs->ier_eoc.mask);
511 * @adc: stm32 adc instance
513 static void stm32_adc_conv_irq_disable(struct stm32_adc *adc)
515 stm32_adc_clr_bits(adc, adc->cfg->regs->ier_eoc.reg,
516 adc->cfg->regs->ier_eoc.mask);
519 static void stm32_adc_ovr_irq_enable(struct stm32_adc *adc)
521 stm32_adc_set_bits(adc, adc->cfg->regs->ier_ovr.reg,
522 adc->cfg->regs->ier_ovr.mask);
525 static void stm32_adc_ovr_irq_disable(struct stm32_adc *adc)
527 stm32_adc_clr_bits(adc, adc->cfg->regs->ier_ovr.reg,
528 adc->cfg->regs->ier_ovr.mask);
531 static void stm32_adc_set_res(struct stm32_adc *adc)
533 const struct stm32_adc_regs *res = &adc->cfg->regs->res;
536 val = stm32_adc_readl(adc, res->reg);
537 val = (val & ~res->mask) | (adc->res << res->shift);
538 stm32_adc_writel(adc, res->reg, val);
544 struct stm32_adc *adc = iio_priv(indio_dev);
546 if (adc->cfg->unprepare)
547 adc->cfg->unprepare(indio_dev);
549 if (adc->clk)
550 clk_disable_unprepare(adc->clk);
558 struct stm32_adc *adc = iio_priv(indio_dev);
561 if (adc->clk) {
562 ret = clk_prepare_enable(adc->clk);
567 stm32_adc_set_res(adc);
569 if (adc->cfg->prepare) {
570 ret = adc->cfg->prepare(indio_dev);
578 if (adc->clk)
579 clk_disable_unprepare(adc->clk);
596 struct stm32_adc *adc = iio_priv(indio_dev);
598 stm32_adc_set_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN);
601 stm32_adc_set_bits(adc, STM32F4_ADC_CR2,
604 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_EOCS | STM32F4_ADON);
610 if (!(stm32_adc_readl(adc, STM32F4_ADC_CR2) & STM32F4_EXTEN_MASK))
611 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_SWSTART);
616 struct stm32_adc *adc = iio_priv(indio_dev);
618 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, STM32F4_EXTEN_MASK);
619 stm32_adc_clr_bits(adc, STM32F4_ADC_SR, STM32F4_STRT);
621 stm32_adc_clr_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN);
622 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2,
628 struct stm32_adc *adc = iio_priv(indio_dev);
630 stm32_adc_clr_bits(adc, adc->cfg->regs->isr_eoc.reg, msk);
635 struct stm32_adc *adc = iio_priv(indio_dev);
645 spin_lock_irqsave(&adc->lock, flags);
646 val = stm32_adc_readl(adc, STM32H7_ADC_CFGR);
648 stm32_adc_writel(adc, STM32H7_ADC_CFGR, val);
649 spin_unlock_irqrestore(&adc->lock, flags);
651 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTART);
656 struct stm32_adc *adc = iio_priv(indio_dev);
660 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTP);
668 stm32_adc_clr_bits(adc, STM32H7_ADC_CFGR, STM32H7_DMNGT_MASK);
673 struct stm32_adc *adc = iio_priv(indio_dev);
675 stm32_adc_set_bits(adc, adc->cfg->regs->isr_eoc.reg, msk);
680 struct stm32_adc *adc = iio_priv(indio_dev);
685 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD);
686 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADVREGEN);
688 if (adc->common->rate > STM32H7_BOOST_CLKRATE)
689 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST);
692 if (!adc->cfg->has_vregready) {
701 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD);
708 static void stm32h7_adc_enter_pwr_down(struct stm32_adc *adc)
710 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST);
713 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD);
718 struct stm32_adc *adc = iio_priv(indio_dev);
722 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADEN);
724 /* Poll for ADRDY to be set (after adc startup time) */
729 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS);
733 stm32_adc_set_bits(adc, STM32H7_ADC_ISR, STM32H7_ADRDY);
741 struct stm32_adc *adc = iio_priv(indio_dev);
746 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS);
761 struct stm32_adc *adc = iio_priv(indio_dev);
769 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask);
780 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2);
781 adc->cal.lincalfact[i] = (val & STM32H7_LINCALFACT_MASK);
782 adc->cal.lincalfact[i] >>= STM32H7_LINCALFACT_SHIFT;
788 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT);
789 adc->cal.calfact_s = (val & STM32H7_CALFACT_S_MASK);
790 adc->cal.calfact_s >>= STM32H7_CALFACT_S_SHIFT;
791 adc->cal.calfact_d = (val & STM32H7_CALFACT_D_MASK);
792 adc->cal.calfact_d >>= STM32H7_CALFACT_D_SHIFT;
793 adc->cal.calibrated = true;
805 struct stm32_adc *adc = iio_priv(indio_dev);
809 val = (adc->cal.calfact_s << STM32H7_CALFACT_S_SHIFT) |
810 (adc->cal.calfact_d << STM32H7_CALFACT_D_SHIFT);
811 stm32_adc_writel(adc, STM32H7_ADC_CALFACT, val);
820 val = adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT;
821 stm32_adc_writel(adc, STM32H7_ADC_CALFACT2, val);
822 stm32_adc_set_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask);
838 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask);
846 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2);
847 if (val != adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT) {
878 struct stm32_adc *adc = iio_priv(indio_dev);
882 if (adc->cal.calibrated)
890 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALDIF);
891 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALLIN);
894 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL);
909 stm32_adc_set_bits(adc, STM32H7_ADC_CR,
911 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL);
921 stm32_adc_clr_bits(adc, STM32H7_ADC_CR,
940 struct stm32_adc *adc = iio_priv(indio_dev);
952 stm32_adc_writel(adc, STM32H7_ADC_DIFSEL, adc->difsel);
966 stm32_adc_writel(adc, STM32H7_ADC_PCSEL, adc->pcsel);
973 stm32h7_adc_enter_pwr_down(adc);
980 struct stm32_adc *adc = iio_priv(indio_dev);
982 stm32_adc_writel(adc, STM32H7_ADC_PCSEL, 0);
984 stm32h7_adc_enter_pwr_down(adc);
1001 struct stm32_adc *adc = iio_priv(indio_dev);
1002 const struct stm32_adc_regs *sqr = adc->cfg->regs->sqr;
1008 stm32_adc_writel(adc, adc->cfg->regs->smpr[0], adc->smpr_val[0]);
1009 stm32_adc_writel(adc, adc->cfg->regs->smpr[1], adc->smpr_val[1]);
1024 val = stm32_adc_readl(adc, sqr[i].reg);
1027 stm32_adc_writel(adc, sqr[i].reg, val);
1034 val = stm32_adc_readl(adc, sqr[0].reg);
1037 stm32_adc_writel(adc, sqr[0].reg, val);
1052 struct stm32_adc *adc = iio_priv(indio_dev);
1056 for (i = 0; adc->cfg->trigs[i].name; i++) {
1063 !strcmp(adc->cfg->trigs[i].name, trig->name)) {
1064 return adc->cfg->trigs[i].extsel;
1083 struct stm32_adc *adc = iio_priv(indio_dev);
1095 exten = adc->trigger_polarity + STM32_EXTEN_HWTRIG_RISING_EDGE;
1098 spin_lock_irqsave(&adc->lock, flags);
1099 val = stm32_adc_readl(adc, adc->cfg->regs->exten.reg);
1100 val &= ~(adc->cfg->regs->exten.mask | adc->cfg->regs->extsel.mask);
1101 val |= exten << adc->cfg->regs->exten.shift;
1102 val |= extsel << adc->cfg->regs->extsel.shift;
1103 stm32_adc_writel(adc, adc->cfg->regs->exten.reg, val);
1104 spin_unlock_irqrestore(&adc->lock, flags);
1113 struct stm32_adc *adc = iio_priv(indio_dev);
1115 adc->trigger_polarity = type;
1123 struct stm32_adc *adc = iio_priv(indio_dev);
1125 return adc->trigger_polarity;
1155 struct stm32_adc *adc = iio_priv(indio_dev);
1157 const struct stm32_adc_regspec *regs = adc->cfg->regs;
1162 reinit_completion(&adc->completion);
1164 adc->bufi = 0;
1173 stm32_adc_writel(adc, regs->smpr[0], adc->smpr_val[0]);
1174 stm32_adc_writel(adc, regs->smpr[1], adc->smpr_val[1]);
1177 val = stm32_adc_readl(adc, regs->sqr[1].reg);
1180 stm32_adc_writel(adc, regs->sqr[1].reg, val);
1183 stm32_adc_clr_bits(adc, regs->sqr[0].reg, regs->sqr[0].mask);
1186 stm32_adc_clr_bits(adc, regs->exten.reg, regs->exten.mask);
1188 stm32_adc_conv_irq_enable(adc);
1190 adc->cfg->start_conv(indio_dev, false);
1193 &adc->completion, STM32_ADC_TIMEOUT);
1199 *res = adc->buffer[0];
1203 adc->cfg->stop_conv(indio_dev);
1205 stm32_adc_conv_irq_disable(adc);
1217 struct stm32_adc *adc = iio_priv(indio_dev);
1234 *val = adc->common->vref_mv * 2;
1237 *val = adc->common->vref_mv;
1257 struct stm32_adc *adc = iio_priv(indio_dev);
1259 adc->cfg->irq_clear(indio_dev, msk);
1265 struct stm32_adc *adc = iio_priv(indio_dev);
1266 const struct stm32_adc_regspec *regs = adc->cfg->regs;
1267 u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg);
1276 adc->cfg->stop_conv(indio_dev);
1288 struct stm32_adc *adc = iio_priv(indio_dev);
1289 const struct stm32_adc_regspec *regs = adc->cfg->regs;
1290 u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg);
1300 stm32_adc_ovr_irq_disable(adc);
1301 stm32_adc_conv_irq_disable(adc);
1307 adc->buffer[adc->bufi] = stm32_adc_readw(adc, regs->dr);
1309 adc->bufi++;
1310 if (adc->bufi >= adc->num_conv) {
1311 stm32_adc_conv_irq_disable(adc);
1315 complete(&adc->completion);
1324 * stm32_adc_validate_trigger() - validate trigger for stm32 adc
1328 * Returns: 0 if trig matches one of the triggers registered by stm32 adc
1339 struct stm32_adc *adc = iio_priv(indio_dev);
1350 adc->rx_buf_sz = min(rx_buf_sz, watermark * 2 * adc->num_conv);
1358 struct stm32_adc *adc = iio_priv(indio_dev);
1368 adc->num_conv = bitmap_weight(scan_mask, indio_dev->masklength);
1407 struct stm32_adc *adc = iio_priv(indio_dev);
1418 stm32_adc_writel(adc, reg, writeval);
1420 *readval = stm32_adc_readl(adc, reg);
1437 static unsigned int stm32_adc_dma_residue(struct stm32_adc *adc)
1442 status = dmaengine_tx_status(adc->dma_chan,
1443 adc->dma_chan->cookie,
1447 unsigned int i = adc->rx_buf_sz - state.residue;
1451 if (i >= adc->bufi)
1452 size = i - adc->bufi;
1454 size = adc->rx_buf_sz + i - adc->bufi;
1465 struct stm32_adc *adc = iio_priv(indio_dev);
1466 int residue = stm32_adc_dma_residue(adc);
1477 dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi);
1480 u16 *buffer = (u16 *)&adc->rx_buf[adc->bufi];
1485 adc->bufi += indio_dev->scan_bytes;
1486 if (adc->bufi >= adc->rx_buf_sz)
1487 adc->bufi = 0;
1493 struct stm32_adc *adc = iio_priv(indio_dev);
1498 if (!adc->dma_chan)
1502 adc->rx_buf_sz, adc->rx_buf_sz / 2);
1505 desc = dmaengine_prep_dma_cyclic(adc->dma_chan,
1506 adc->rx_dma_buf,
1507 adc->rx_buf_sz, adc->rx_buf_sz / 2,
1519 dmaengine_terminate_sync(adc->dma_chan);
1524 dma_async_issue_pending(adc->dma_chan);
1531 struct stm32_adc *adc = iio_priv(indio_dev);
1553 /* Reset adc buffer index */
1554 adc->bufi = 0;
1556 stm32_adc_ovr_irq_enable(adc);
1558 if (!adc->dma_chan)
1559 stm32_adc_conv_irq_enable(adc);
1561 adc->cfg->start_conv(indio_dev, !!adc->dma_chan);
1576 struct stm32_adc *adc = iio_priv(indio_dev);
1579 adc->cfg->stop_conv(indio_dev);
1580 if (!adc->dma_chan)
1581 stm32_adc_conv_irq_disable(adc);
1583 stm32_adc_ovr_irq_disable(adc);
1585 if (adc->dma_chan)
1586 dmaengine_terminate_sync(adc->dma_chan);
1606 struct stm32_adc *adc = iio_priv(indio_dev);
1608 dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi);
1610 if (!adc->dma_chan) {
1612 adc->bufi = 0;
1613 iio_push_to_buffers_with_timestamp(indio_dev, adc->buffer,
1616 int residue = stm32_adc_dma_residue(adc);
1619 u16 *buffer = (u16 *)&adc->rx_buf[adc->bufi];
1624 adc->bufi += indio_dev->scan_bytes;
1625 if (adc->bufi >= adc->rx_buf_sz)
1626 adc->bufi = 0;
1633 if (!adc->dma_chan)
1634 stm32_adc_conv_irq_enable(adc);
1653 struct stm32_adc *adc = iio_priv(indio_dev);
1658 res = adc->cfg->adc_info->resolutions[0];
1660 for (i = 0; i < adc->cfg->adc_info->num_res; i++)
1661 if (res == adc->cfg->adc_info->resolutions[i])
1663 if (i >= adc->cfg->adc_info->num_res) {
1669 adc->res = i;
1674 static void stm32_adc_smpr_init(struct stm32_adc *adc, int channel, u32 smp_ns)
1676 const struct stm32_adc_regs *smpr = &adc->cfg->regs->smp_bits[channel];
1681 period_ns = NSEC_PER_SEC / adc->common->rate;
1683 if ((period_ns * adc->cfg->smp_cycles[smp]) >= smp_ns)
1689 adc->smpr_val[r] = (adc->smpr_val[r] & ~mask) | (smp << shift);
1696 struct stm32_adc *adc = iio_priv(indio_dev);
1697 char *name = adc->chan_name[vinp];
1715 chan->scan_type.realbits = adc->cfg->adc_info->resolutions[adc->res];
1720 adc->pcsel |= BIT(chan->channel);
1723 adc->difsel |= BIT(chan->channel);
1725 adc->pcsel |= BIT(chan->channel2);
1732 struct stm32_adc *adc = iio_priv(indio_dev);
1733 const struct stm32_adc_info *adc_info = adc->cfg->adc_info;
1741 ret = of_property_count_u32_elems(node, "st,adc-channels");
1743 dev_err(&indio_dev->dev, "Bad st,adc-channels?\n");
1749 ret = of_property_count_elems_of_size(node, "st,adc-diff-channels",
1752 dev_err(&indio_dev->dev, "Bad st,adc-diff-channels?\n");
1759 ret = of_property_read_u32_array(node, "st,adc-diff-channels",
1782 of_property_for_each_u32(node, "st,adc-channels", prop, cur, val) {
1824 stm32_adc_smpr_init(adc, channels[i].channel, smp);
1835 struct stm32_adc *adc = iio_priv(indio_dev);
1839 adc->dma_chan = dma_request_chan(dev, "rx");
1840 if (IS_ERR(adc->dma_chan)) {
1841 ret = PTR_ERR(adc->dma_chan);
1847 adc->dma_chan = NULL;
1851 adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev,
1853 &adc->rx_dma_buf, GFP_KERNEL);
1854 if (!adc->rx_buf) {
1861 config.src_addr = (dma_addr_t)adc->common->phys_base;
1862 config.src_addr += adc->offset + adc->cfg->regs->dr;
1865 ret = dmaengine_slave_config(adc->dma_chan, &config);
1872 dma_free_coherent(adc->dma_chan->device->dev, STM32_DMA_BUFFER_SIZE,
1873 adc->rx_buf, adc->rx_dma_buf);
1875 dma_release_channel(adc->dma_chan);
1885 struct stm32_adc *adc;
1891 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc));
1895 adc = iio_priv(indio_dev);
1896 adc->common = dev_get_drvdata(pdev->dev.parent);
1897 spin_lock_init(&adc->lock);
1898 init_completion(&adc->completion);
1899 adc->cfg = (const struct stm32_adc_cfg *)
1909 ret = of_property_read_u32(pdev->dev.of_node, "reg", &adc->offset);
1915 adc->irq = platform_get_irq(pdev, 0);
1916 if (adc->irq < 0)
1917 return adc->irq;
1919 ret = devm_request_threaded_irq(&pdev->dev, adc->irq, stm32_adc_isr,
1927 adc->clk = devm_clk_get(&pdev->dev, NULL);
1928 if (IS_ERR(adc->clk)) {
1929 ret = PTR_ERR(adc->clk);
1930 if (ret == -ENOENT && !adc->cfg->clk_required) {
1931 adc->clk = NULL;
1950 if (!adc->dma_chan)
1961 /* Get stm32-adc-core PM online */
1993 if (adc->dma_chan) {
1994 dma_free_coherent(adc->dma_chan->device->dev,
1996 adc->rx_buf, adc->rx_dma_buf);
1997 dma_release_channel(adc->dma_chan);
2006 struct stm32_adc *adc = iio_priv(indio_dev);
2015 if (adc->dma_chan) {
2016 dma_free_coherent(adc->dma_chan->device->dev,
2018 adc->rx_buf, adc->rx_dma_buf);
2019 dma_release_channel(adc->dma_chan);
2112 { .compatible = "st,stm32f4-adc", .data = (void *)&stm32f4_adc_cfg },
2113 { .compatible = "st,stm32h7-adc", .data = (void *)&stm32h7_adc_cfg },
2114 { .compatible = "st,stm32mp1-adc", .data = (void *)&stm32mp1_adc_cfg },
2123 .name = "stm32-adc",
2133 MODULE_ALIAS("platform:stm32-adc");