Lines Matching defs:channel
113 u32 channel;
144 .channel = (_idx), \
192 * Before sample set, disable channel A,B,C,D. Here we
222 /* enable channel A,B,C,D interrupt */
235 u32 channel;
237 channel = info->channel;
239 /* the channel choose single conversion, and enable average mode */
245 * physical channel 0 chose logical channel A
246 * physical channel 1 chose logical channel B
247 * physical channel 2 chose logical channel C
248 * physical channel 3 chose logical channel D
250 cfg1 |= IMX7D_REG_ADC_CH_CFG1_CHANNEL_SEL(channel);
254 * channel chosen
256 cfg2 = readl(info->regs + IMX7D_EACH_CHANNEL_REG_OFFSET * channel +
263 * the channel chosen
265 writel(cfg2, info->regs + IMX7D_EACH_CHANNEL_REG_OFFSET * channel +
267 writel(cfg1, info->regs + IMX7D_EACH_CHANNEL_REG_OFFSET * channel);
290 u32 channel;
298 channel = chan->channel & 0x03;
299 info->channel = channel;
334 u32 channel;
337 channel = info->channel & 0x03;
340 * channel A and B conversion result share one register,
341 * bit[27~16] is the channel B conversion result,
342 * bit[11~0] is the channel A conversion result.
343 * channel C and D is the same.
345 if (channel < 2)
349 if (channel & 0x1) /* channel B or D */
351 else /* channel A or C */
370 * 0 to the related bit. Here we clear the channel A/B/C/D
378 * If the channel A/B/C/D conversion timeout, report it and clear these