Lines Matching refs:info
160 void (*init_hw)(struct exynos_adc *info);
161 void (*exit_hw)(struct exynos_adc *info);
162 void (*clear_irq)(struct exynos_adc *info);
163 void (*start_conv)(struct exynos_adc *info, unsigned long addr);
166 static void exynos_adc_unprepare_clk(struct exynos_adc *info)
168 if (info->data->needs_sclk)
169 clk_unprepare(info->sclk);
170 clk_unprepare(info->clk);
173 static int exynos_adc_prepare_clk(struct exynos_adc *info)
177 ret = clk_prepare(info->clk);
179 dev_err(info->dev, "failed preparing adc clock: %d\n", ret);
183 if (info->data->needs_sclk) {
184 ret = clk_prepare(info->sclk);
186 clk_unprepare(info->clk);
187 dev_err(info->dev,
196 static void exynos_adc_disable_clk(struct exynos_adc *info)
198 if (info->data->needs_sclk)
199 clk_disable(info->sclk);
200 clk_disable(info->clk);
203 static int exynos_adc_enable_clk(struct exynos_adc *info)
207 ret = clk_enable(info->clk);
209 dev_err(info->dev, "failed enabling adc clock: %d\n", ret);
213 if (info->data->needs_sclk) {
214 ret = clk_enable(info->sclk);
216 clk_disable(info->clk);
217 dev_err(info->dev,
226 static void exynos_adc_v1_init_hw(struct exynos_adc *info)
230 if (info->data->needs_adc_phy)
231 regmap_write(info->pmu_map, info->data->phy_offset, 1);
238 writel(con1, ADC_V1_CON(info->regs));
241 writel(info->delay, ADC_V1_DLY(info->regs));
244 static void exynos_adc_v1_exit_hw(struct exynos_adc *info)
248 if (info->data->needs_adc_phy)
249 regmap_write(info->pmu_map, info->data->phy_offset, 0);
251 con = readl(ADC_V1_CON(info->regs));
253 writel(con, ADC_V1_CON(info->regs));
256 static void exynos_adc_v1_clear_irq(struct exynos_adc *info)
258 writel(1, ADC_V1_INTCLR(info->regs));
261 static void exynos_adc_v1_start_conv(struct exynos_adc *info,
266 writel(addr, ADC_V1_MUX(info->regs));
268 con1 = readl(ADC_V1_CON(info->regs));
269 writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
307 static void exynos_adc_s3c2416_start_conv(struct exynos_adc *info,
313 con1 = readl(ADC_V1_CON(info->regs));
315 writel(con1, ADC_V1_CON(info->regs));
318 writel(addr, ADC_S3C2410_MUX(info->regs));
320 con1 = readl(ADC_V1_CON(info->regs));
321 writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
333 static void exynos_adc_s3c2443_start_conv(struct exynos_adc *info,
339 writel(addr, ADC_S3C2410_MUX(info->regs));
341 con1 = readl(ADC_V1_CON(info->regs));
342 writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
354 static void exynos_adc_s3c64xx_start_conv(struct exynos_adc *info,
359 con1 = readl(ADC_V1_CON(info->regs));
362 writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
384 static void exynos_adc_v2_init_hw(struct exynos_adc *info)
388 if (info->data->needs_adc_phy)
389 regmap_write(info->pmu_map, info->data->phy_offset, 1);
392 writel(con1, ADC_V2_CON1(info->regs));
396 writel(con2, ADC_V2_CON2(info->regs));
399 writel(1, ADC_V2_INT_EN(info->regs));
402 static void exynos_adc_v2_exit_hw(struct exynos_adc *info)
406 if (info->data->needs_adc_phy)
407 regmap_write(info->pmu_map, info->data->phy_offset, 0);
409 con = readl(ADC_V2_CON1(info->regs));
411 writel(con, ADC_V2_CON1(info->regs));
414 static void exynos_adc_v2_clear_irq(struct exynos_adc *info)
416 writel(1, ADC_V2_INT_ST(info->regs));
419 static void exynos_adc_v2_start_conv(struct exynos_adc *info,
424 con2 = readl(ADC_V2_CON2(info->regs));
427 writel(con2, ADC_V2_CON2(info->regs));
429 con1 = readl(ADC_V2_CON1(info->regs));
430 writel(con1 | ADC_CON_EN_START, ADC_V2_CON1(info->regs));
458 static void exynos_adc_exynos7_init_hw(struct exynos_adc *info)
463 writel(con1, ADC_V2_CON1(info->regs));
465 con2 = readl(ADC_V2_CON2(info->regs));
468 writel(con2, ADC_V2_CON2(info->regs));
471 writel(1, ADC_V2_INT_EN(info->regs));
537 struct exynos_adc *info = iio_priv(indio_dev);
542 ret = regulator_get_voltage(info->vdd);
548 *val2 = info->data->mask;
555 mutex_lock(&info->lock);
556 reinit_completion(&info->completion);
559 if (info->data->start_conv)
560 info->data->start_conv(info, chan->address);
562 timeout = wait_for_completion_timeout(&info->completion,
566 if (info->data->init_hw)
567 info->data->init_hw(info);
570 *val = info->value;
575 mutex_unlock(&info->lock);
582 struct exynos_adc *info = iio_priv(indio_dev);
586 mutex_lock(&info->lock);
587 info->read_ts = true;
589 reinit_completion(&info->completion);
592 ADC_V1_TSC(info->regs));
595 info->data->start_conv(info, ADC_S3C2410_MUX_TS);
597 timeout = wait_for_completion_timeout(&info->completion,
601 if (info->data->init_hw)
602 info->data->init_hw(info);
605 *x = info->ts_x;
606 *y = info->ts_y;
610 info->read_ts = false;
611 mutex_unlock(&info->lock);
618 struct exynos_adc *info = dev_id;
619 u32 mask = info->data->mask;
622 if (info->read_ts) {
623 info->ts_x = readl(ADC_V1_DATX(info->regs));
624 info->ts_y = readl(ADC_V1_DATY(info->regs));
625 writel(ADC_TSC_WAIT4INT | ADC_S3C2443_TSC_UD_SEN, ADC_V1_TSC(info->regs));
627 info->value = readl(ADC_V1_DATX(info->regs)) & mask;
631 if (info->data->clear_irq)
632 info->data->clear_irq(info);
634 complete(&info->completion);
648 struct exynos_adc *info = dev_id;
649 struct iio_dev *dev = dev_get_drvdata(info->dev);
654 while (info->input->users) {
661 input_report_key(info->input, BTN_TOUCH, 0);
662 input_sync(info->input);
666 input_report_abs(info->input, ABS_X, x & ADC_DATX_MASK);
667 input_report_abs(info->input, ABS_Y, y & ADC_DATY_MASK);
668 input_report_key(info->input, BTN_TOUCH, 1);
669 input_sync(info->input);
674 writel(0, ADC_V1_CLRINTPNDNUP(info->regs));
683 struct exynos_adc *info = iio_priv(indio_dev);
688 *readval = readl(info->regs + reg);
732 struct exynos_adc *info = input_get_drvdata(dev);
734 enable_irq(info->tsirq);
741 struct exynos_adc *info = input_get_drvdata(dev);
743 disable_irq(info->tsirq);
746 static int exynos_adc_ts_init(struct exynos_adc *info)
750 if (info->tsirq <= 0)
753 info->input = input_allocate_device();
754 if (!info->input)
757 info->input->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS);
758 info->input->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
760 input_set_abs_params(info->input, ABS_X, 0, 0x3FF, 0, 0);
761 input_set_abs_params(info->input, ABS_Y, 0, 0x3FF, 0, 0);
763 info->input->name = "S3C24xx TouchScreen";
764 info->input->id.bustype = BUS_HOST;
765 info->input->open = exynos_adc_ts_open;
766 info->input->close = exynos_adc_ts_close;
768 input_set_drvdata(info->input, info);
770 ret = input_register_device(info->input);
772 input_free_device(info->input);
776 disable_irq(info->tsirq);
777 ret = request_threaded_irq(info->tsirq, NULL, exynos_ts_isr,
778 IRQF_ONESHOT, "touchscreen", info);
780 input_unregister_device(info->input);
787 struct exynos_adc *info = NULL;
801 info = iio_priv(indio_dev);
803 info->data = exynos_adc_get_data(pdev);
804 if (!info->data) {
809 info->regs = devm_platform_ioremap_resource(pdev, 0);
810 if (IS_ERR(info->regs))
811 return PTR_ERR(info->regs);
814 if (info->data->needs_adc_phy) {
815 info->pmu_map = syscon_regmap_lookup_by_phandle(
818 if (IS_ERR(info->pmu_map)) {
820 return PTR_ERR(info->pmu_map);
833 info->irq = irq;
840 info->tsirq = irq;
842 info->tsirq = -1;
845 info->dev = &pdev->dev;
847 init_completion(&info->completion);
849 info->clk = devm_clk_get(&pdev->dev, "adc");
850 if (IS_ERR(info->clk)) {
852 PTR_ERR(info->clk));
853 return PTR_ERR(info->clk);
856 if (info->data->needs_sclk) {
857 info->sclk = devm_clk_get(&pdev->dev, "sclk");
858 if (IS_ERR(info->sclk)) {
861 PTR_ERR(info->sclk));
862 return PTR_ERR(info->sclk);
866 info->vdd = devm_regulator_get(&pdev->dev, "vdd");
867 if (IS_ERR(info->vdd))
868 return dev_err_probe(&pdev->dev, PTR_ERR(info->vdd),
871 ret = regulator_enable(info->vdd);
875 ret = exynos_adc_prepare_clk(info);
879 ret = exynos_adc_enable_clk(info);
886 indio_dev->info = &exynos_adc_iio_info;
889 indio_dev->num_channels = info->data->num_channels;
891 mutex_init(&info->lock);
893 ret = request_irq(info->irq, exynos_adc_isr,
894 0, dev_name(&pdev->dev), info);
897 info->irq);
905 if (info->data->init_hw)
906 info->data->init_hw(info);
909 info->delay = pdata->delay;
911 info->delay = 10000;
914 ret = exynos_adc_ts_init(info);
930 input_unregister_device(info->input);
931 free_irq(info->tsirq, info);
936 free_irq(info->irq, info);
938 if (info->data->exit_hw)
939 info->data->exit_hw(info);
940 exynos_adc_disable_clk(info);
942 exynos_adc_unprepare_clk(info);
944 regulator_disable(info->vdd);
951 struct exynos_adc *info = iio_priv(indio_dev);
953 if (IS_REACHABLE(CONFIG_INPUT) && info->input) {
954 free_irq(info->tsirq, info);
955 input_unregister_device(info->input);
960 free_irq(info->irq, info);
961 if (info->data->exit_hw)
962 info->data->exit_hw(info);
963 exynos_adc_disable_clk(info);
964 exynos_adc_unprepare_clk(info);
965 regulator_disable(info->vdd);
974 struct exynos_adc *info = iio_priv(indio_dev);
976 if (info->data->exit_hw)
977 info->data->exit_hw(info);
978 exynos_adc_disable_clk(info);
979 regulator_disable(info->vdd);
987 struct exynos_adc *info = iio_priv(indio_dev);
990 ret = regulator_enable(info->vdd);
994 ret = exynos_adc_enable_clk(info);
998 if (info->data->init_hw)
999 info->data->init_hw(info);