Lines Matching refs:clock_sel
188 u8 clock_sel;
325 unsigned int clock_sel;
327 clock_sel = AD7192_CLK_INT;
332 clock_sel = AD7192_CLK_INT_CO;
335 clock_sel = AD7192_CLK_EXT_MCLK1_2;
337 clock_sel = AD7192_CLK_EXT_MCLK2;
340 return clock_sel;
369 AD7192_MODE_CLKSRC(st->clock_sel) |
984 st->clock_sel = ad7192_of_clock_select(st);
986 if (st->clock_sel == AD7192_CLK_EXT_MCLK1_2 ||
987 st->clock_sel == AD7192_CLK_EXT_MCLK2) {
1011 if (st->clock_sel == AD7192_CLK_EXT_MCLK1_2 ||
1012 st->clock_sel == AD7192_CLK_EXT_MCLK2)
1030 if (st->clock_sel == AD7192_CLK_EXT_MCLK1_2 ||
1031 st->clock_sel == AD7192_CLK_EXT_MCLK2)