Lines Matching refs:fclk
265 unsigned int fclk, odr_sel_bits;
268 fclk = clk_get_rate(st->mclk);
276 odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32);
289 DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32);
662 unsigned int val, fclk, power_mode;
665 fclk = clk_get_rate(st->mclk);
666 if (!fclk)
672 fclk);
673 if (fclk != ad7124_master_clk_freq_hz[power_mode]) {
674 ret = clk_set_rate(st->mclk, fclk);