Lines Matching defs:timings
59 u32 timings[4];
132 * The "PIO" register controls PIO and MDMA timings, the "ULTRA"
133 * register controls the UDMA timings. At least, it seems bit 0
188 * is used to reach long timings used in this mode.
216 /* Rounded Multiword DMA timings
267 /* KeyLargo ATA-4 Ultra DMA timings (rounded) */
281 /* UniNorth 2 ATA/100 timings */
406 * Apply the timings of the proper unit (master/slave) to the shared
416 writel(pmif->timings[1], PMAC_IDE_REG(IDE_TIMING_CONFIG));
418 writel(pmif->timings[0], PMAC_IDE_REG(IDE_TIMING_CONFIG));
423 * Apply the timings of the proper unit (master/slave) to the shared
433 writel(pmif->timings[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
434 writel(pmif->timings[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
436 writel(pmif->timings[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
437 writel(pmif->timings[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
490 * Old tuning functions (called on hdparm -p), sets up drive PIO timings
497 u32 *timings, t;
503 timings = &pmif->timings[drive->dn & 1];
504 t = *timings;
564 drive->name, pio, *timings);
567 *timings = t;
572 * Calculate KeyLargo ATA/66 UDMA timings
575 set_timings_udma_ata4(u32 *timings, u8 speed)
586 *timings = ((*timings) & ~(TR_66_UDMA_MASK | TR_66_MDMA_MASK)) |
593 speed & 0xf, *timings);
600 * Calculate Kauai ATA/100 UDMA timings
618 * Calculate Shasta ATA/133 UDMA timings
636 * Calculate MDMA timings for all cells
639 set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2,
702 *timings = ((*timings) & ~TR_133_PIOREG_MDMA_MASK) | tr;
710 *timings = ((*timings) & ~TR_100_PIOREG_MDMA_MASK) | tr;
723 *timings = ((*timings) & ~(TR_66_MDMA_MASK | TR_66_UDMA_MASK)) |
736 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
760 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
764 *timings |= TR_33_MDMA_HALFTICK;
769 drive->name, speed & 0xf, *timings);
777 u32 *timings, *timings2, tl[2];
781 timings = &pmif->timings[unit];
782 timings2 = &pmif->timings[unit+2];
784 /* Copy timings to local image */
785 tl[0] = *timings;
804 /* Apply timings to controller */
805 *timings = tl[0];
842 pmif->timings[0] = pmif->timings[1] = value;
843 pmif->timings[2] = pmif->timings[3] = value2;
856 /* We clear the timings */
857 pmif->timings[0] = 0;
858 pmif->timings[1] = 0;
902 /* Sanitize drive timings */
1065 /* Make sure we have sane timings */
1526 * Prepare a DMA transfer. We build the DMA table, adjust the timings for
1540 if (ata4 && (pmif->timings[unit] & TR_66_UDMA_EN)) {
1541 writel(pmif->timings[unit] + (write ? 0 : 0x00800000UL),