Lines Matching refs:cycle
72 u16 cycle = 0;
76 cycle = id[ATA_ID_EIDE_PIO_IORDY];
78 cycle = id[ATA_ID_EIDE_PIO];
81 if (pio < 3 && cycle < t->cycle)
82 cycle = 0; /* use standard timing */
86 cycle = 0;
89 return cycle ? cycle : t->cycle;
105 q->cycle = EZ(t->cycle, T);
125 m->cycle = max(a->cycle, b->cycle);
151 * PIO/MWDMA cycle timing.
158 p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO];
161 p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO_IORDY];
163 p.cycle = id[ATA_ID_EIDE_DMA_MIN];
176 * DMA cycle timing is slower/equal than the current PIO timing.
184 * Lengthen active & recovery time so that cycle time is correct.
191 if (t->active + t->recover < t->cycle) {
192 t->active += (t->cycle - (t->active + t->recover)) / 2;
193 t->recover = t->cycle - t->active;