Lines Matching defs:clock
30 * - use pll if we don't have a clock table. added a 66MHz table that's
52 * Added support for 372N clocking and clock switching. The 372N needs
58 * - fix the clock turnaround code: it was writing to the wrong ports when
59 * called for the secondary channel, caching the current clock mode per-
63 * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used
99 * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
106 * - get rid of the constant thresholds in the HPT37x PCI clock detection code,
107 * switch to calculating PCI clock frequency based on the chip's base DPLL
109 * - switch to using the DPLL clock and enable UltraATA/133 mode by default on
112 * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
113 * also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;
115 * the register setting lists into the table indexed by the clock selected
218 /* Key for bus clock timings
230 * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock.
375 /* Supported ATA clock frequencies */
400 u8 dpll_clk; /* DPLL clock in MHz */
401 u8 pci_clk; /* PCI clock in MHz */
403 u8 clock; /* ATA clock selected */
625 return info->timings->clock_table[info->clock][i];
789 * hpt3xxn_set_clock - perform clock switching dance
793 * Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
808 /* Switch clock and reset channels */
833 * We need it because of the clock switching.
911 u8 pci_clk, dpll_clk = 0; /* PCI and DPLL clock in MHz */
913 enum ata_clock clock;
923 * First, try to estimate the PCI clock frequency...
943 * Default to PCI clock. Make sure MA15/16 are set to output
950 * the PCI clock frequency according to the following ratio:
982 printk(KERN_WARNING "%s %s: no clock data saved by "
998 /* Clamp PCI clock to bands. */
1016 /* Detect PCI clock by looking at cmd_high_time. */
1031 /* Let's assume we'll use PCI clock for the ATA clock... */
1034 clock = ATA_CLOCK_25MHZ;
1038 clock = ATA_CLOCK_33MHZ;
1041 clock = ATA_CLOCK_40MHZ;
1044 clock = ATA_CLOCK_50MHZ;
1047 clock = ATA_CLOCK_66MHZ;
1052 * Only try the DPLL if we don't have a table for the PCI clock that
1059 if (chip_type >= HPT374 || info->timings->clock_table[clock] == NULL) {
1064 * Select 66 MHz DPLL clock only if UltraATA/133 mode is
1065 * supported/enabled, use 50 MHz DPLL clock otherwise...
1069 clock = ATA_CLOCK_66MHZ;
1072 clock = ATA_CLOCK_50MHZ;
1075 if (info->timings->clock_table[clock] == NULL) {
1081 /* Select the DPLL clock. */
1085 * Adjust the DPLL based upon PCI clock, enable it,
1095 * See if it'll settle at a fractionally different clock
1108 printk(KERN_INFO "%s %s: using %d MHz DPLL clock\n",
1114 printk(KERN_INFO "%s %s: using %d MHz PCI clock\n",
1118 /* Store the clock frequencies. */
1121 info->clock = clock;
1138 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
1142 if (chip_type == HPT371N && clock == ATA_CLOCK_66MHZ)
1208 * - on 33 MHz PCI we must clock switch
1209 * - on 66 MHz PCI we must NOT use the PCI clock