Lines Matching defs:master
13 #include <linux/i3c/master.h>
296 to_dw_i3c_master(struct i3c_master_controller *master)
298 return container_of(master, struct dw_i3c_master, base);
301 static void dw_i3c_master_disable(struct dw_i3c_master *master)
303 writel(readl(master->regs + DEVICE_CTRL) & ~DEV_CTRL_ENABLE,
304 master->regs + DEVICE_CTRL);
307 static void dw_i3c_master_enable(struct dw_i3c_master *master)
309 writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_ENABLE,
310 master->regs + DEVICE_CTRL);
313 static int dw_i3c_master_get_addr_pos(struct dw_i3c_master *master, u8 addr)
317 for (pos = 0; pos < master->maxdevs; pos++) {
318 if (addr == master->addrs[pos])
325 static int dw_i3c_master_get_free_pos(struct dw_i3c_master *master)
327 if (!(master->free_pos & GENMASK(master->maxdevs - 1, 0)))
330 return ffs(master->free_pos) - 1;
333 static void dw_i3c_master_wr_tx_fifo(struct dw_i3c_master *master,
336 writesl(master->regs + RX_TX_DATA_PORT, bytes, nbytes / 4);
341 writesl(master->regs + RX_TX_DATA_PORT, &tmp, 1);
345 static void dw_i3c_master_read_rx_fifo(struct dw_i3c_master *master,
348 readsl(master->regs + RX_TX_DATA_PORT, bytes, nbytes / 4);
352 readsl(master->regs + RX_TX_DATA_PORT, &tmp, 1);
358 dw_i3c_master_alloc_xfer(struct dw_i3c_master *master, unsigned int ncmds)
378 static void dw_i3c_master_start_xfer_locked(struct dw_i3c_master *master)
380 struct dw_i3c_xfer *xfer = master->xferqueue.cur;
390 dw_i3c_master_wr_tx_fifo(master, cmd->tx_buf, cmd->tx_len);
393 thld_ctrl = readl(master->regs + QUEUE_THLD_CTRL);
396 writel(thld_ctrl, master->regs + QUEUE_THLD_CTRL);
401 writel(cmd->cmd_hi, master->regs + COMMAND_QUEUE_PORT);
402 writel(cmd->cmd_lo, master->regs + COMMAND_QUEUE_PORT);
406 static void dw_i3c_master_enqueue_xfer(struct dw_i3c_master *master,
412 spin_lock_irqsave(&master->xferqueue.lock, flags);
413 if (master->xferqueue.cur) {
414 list_add_tail(&xfer->node, &master->xferqueue.list);
416 master->xferqueue.cur = xfer;
417 dw_i3c_master_start_xfer_locked(master);
419 spin_unlock_irqrestore(&master->xferqueue.lock, flags);
422 static void dw_i3c_master_dequeue_xfer_locked(struct dw_i3c_master *master,
425 if (master->xferqueue.cur == xfer) {
428 master->xferqueue.cur = NULL;
432 master->regs + RESET_CTRL);
434 readl_poll_timeout_atomic(master->regs + RESET_CTRL, status,
441 static void dw_i3c_master_dequeue_xfer(struct dw_i3c_master *master,
446 spin_lock_irqsave(&master->xferqueue.lock, flags);
447 dw_i3c_master_dequeue_xfer_locked(master, xfer);
448 spin_unlock_irqrestore(&master->xferqueue.lock, flags);
451 static void dw_i3c_master_end_xfer_locked(struct dw_i3c_master *master, u32 isr)
453 struct dw_i3c_xfer *xfer = master->xferqueue.cur;
460 nresp = readl(master->regs + QUEUE_STATUS_LEVEL);
467 resp = readl(master->regs + RESPONSE_QUEUE_PORT);
473 dw_i3c_master_read_rx_fifo(master, cmd->rx_buf,
503 dw_i3c_master_dequeue_xfer_locked(master, xfer);
504 writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_RESUME,
505 master->regs + DEVICE_CTRL);
508 xfer = list_first_entry_or_null(&master->xferqueue.list,
514 master->xferqueue.cur = xfer;
515 dw_i3c_master_start_xfer_locked(master);
518 static int dw_i3c_clk_cfg(struct dw_i3c_master *master)
524 core_rate = clk_get_rate(master->core_clk);
539 writel(scl_timing, master->regs + SCL_I3C_PP_TIMING);
541 if (!(readl(master->regs + DEVICE_CTRL) & DEV_CTRL_I2C_SLAVE_PRESENT))
542 writel(BUS_I3C_MST_FREE(lcnt), master->regs + BUS_FREE_TIMING);
546 writel(scl_timing, master->regs + SCL_I3C_OD_TIMING);
556 writel(scl_timing, master->regs + SCL_EXT_LCNT_TIMING);
561 static int dw_i2c_clk_cfg(struct dw_i3c_master *master)
567 core_rate = clk_get_rate(master->core_clk);
577 writel(scl_timing, master->regs + SCL_I2C_FMP_TIMING);
583 writel(scl_timing, master->regs + SCL_I2C_FM_TIMING);
585 writel(BUS_I3C_MST_FREE(lcnt), master->regs + BUS_FREE_TIMING);
586 writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_I2C_SLAVE_PRESENT,
587 master->regs + DEVICE_CTRL);
594 struct dw_i3c_master *master = to_dw_i3c_master(m);
603 ret = dw_i2c_clk_cfg(master);
608 ret = dw_i3c_clk_cfg(master);
616 thld_ctrl = readl(master->regs + QUEUE_THLD_CTRL);
618 writel(thld_ctrl, master->regs + QUEUE_THLD_CTRL);
620 thld_ctrl = readl(master->regs + DATA_BUFFER_THLD_CTRL);
622 writel(thld_ctrl, master->regs + DATA_BUFFER_THLD_CTRL);
624 writel(INTR_ALL, master->regs + INTR_STATUS);
625 writel(INTR_MASTER_MASK, master->regs + INTR_STATUS_EN);
626 writel(INTR_MASTER_MASK, master->regs + INTR_SIGNAL_EN);
633 master->regs + DEVICE_ADDR);
638 ret = i3c_master_set_info(&master->base, &info);
642 writel(IBI_REQ_REJECT_ALL, master->regs + IBI_SIR_REQ_REJECT);
643 writel(IBI_REQ_REJECT_ALL, master->regs + IBI_MR_REQ_REJECT);
646 writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_HOT_JOIN_NACK,
647 master->regs + DEVICE_CTRL);
649 dw_i3c_master_enable(master);
656 struct dw_i3c_master *master = to_dw_i3c_master(m);
658 dw_i3c_master_disable(master);
661 static int dw_i3c_ccc_set(struct dw_i3c_master *master,
669 pos = dw_i3c_master_get_addr_pos(master, ccc->dests[0].addr);
674 xfer = dw_i3c_master_alloc_xfer(master, 1);
691 dw_i3c_master_enqueue_xfer(master, xfer);
693 dw_i3c_master_dequeue_xfer(master, xfer);
704 static int dw_i3c_ccc_get(struct dw_i3c_master *master, struct i3c_ccc_cmd *ccc)
710 pos = dw_i3c_master_get_addr_pos(master, ccc->dests[0].addr);
714 xfer = dw_i3c_master_alloc_xfer(master, 1);
732 dw_i3c_master_enqueue_xfer(master, xfer);
734 dw_i3c_master_dequeue_xfer(master, xfer);
747 struct dw_i3c_master *master = to_dw_i3c_master(m);
754 ret = dw_i3c_ccc_get(master, ccc);
756 ret = dw_i3c_ccc_set(master, ccc);
763 struct dw_i3c_master *master = to_dw_i3c_master(m);
770 olddevs = ~(master->free_pos);
773 for (pos = 0; pos < master->maxdevs; pos++) {
781 master->addrs[pos] = ret;
787 master->regs +
788 DEV_ADDR_TABLE_LOC(master->datstartaddr, pos));
791 xfer = dw_i3c_master_alloc_xfer(master, 1);
795 pos = dw_i3c_master_get_free_pos(master);
798 cmd->cmd_lo = COMMAND_PORT_DEV_COUNT(master->maxdevs - pos) |
805 dw_i3c_master_enqueue_xfer(master, xfer);
807 dw_i3c_master_dequeue_xfer(master, xfer);
809 newdevs = GENMASK(master->maxdevs - cmd->rx_len - 1, 0);
812 for (pos = 0; pos < master->maxdevs; pos++) {
814 i3c_master_add_i3c_dev_locked(m, master->addrs[pos]);
833 struct dw_i3c_master *master = to_dw_i3c_master(m);
841 if (i3c_nxfers > master->caps.cmdfifodepth)
851 if (ntxwords > master->caps.datafifodepth ||
852 nrxwords > master->caps.datafifodepth)
855 xfer = dw_i3c_master_alloc_xfer(master, i3c_nxfers);
886 dw_i3c_master_enqueue_xfer(master, xfer);
888 dw_i3c_master_dequeue_xfer(master, xfer);
901 struct dw_i3c_master *master = to_dw_i3c_master(m);
904 pos = dw_i3c_master_get_free_pos(master);
908 master->regs +
909 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
911 master->addrs[data->index] = 0;
912 master->free_pos |= BIT(data->index);
915 master->addrs[pos] = dev->info.dyn_addr;
916 master->free_pos &= ~BIT(pos);
920 master->regs +
921 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
923 master->addrs[data->index] = dev->info.dyn_addr;
931 struct dw_i3c_master *master = to_dw_i3c_master(m);
935 pos = dw_i3c_master_get_free_pos(master);
944 master->addrs[pos] = dev->info.dyn_addr ? : dev->info.static_addr;
945 master->free_pos &= ~BIT(pos);
948 writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(master->addrs[pos]),
949 master->regs +
950 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
959 struct dw_i3c_master *master = to_dw_i3c_master(m);
962 master->regs +
963 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
966 master->addrs[data->index] = 0;
967 master->free_pos |= BIT(data->index);
977 struct dw_i3c_master *master = to_dw_i3c_master(m);
985 if (i2c_nxfers > master->caps.cmdfifodepth)
995 if (ntxwords > master->caps.datafifodepth ||
996 nrxwords > master->caps.datafifodepth)
999 xfer = dw_i3c_master_alloc_xfer(master, i2c_nxfers);
1026 dw_i3c_master_enqueue_xfer(master, xfer);
1028 dw_i3c_master_dequeue_xfer(master, xfer);
1039 struct dw_i3c_master *master = to_dw_i3c_master(m);
1043 pos = dw_i3c_master_get_free_pos(master);
1052 master->addrs[pos] = dev->addr;
1053 master->free_pos &= ~BIT(pos);
1058 master->regs +
1059 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
1068 struct dw_i3c_master *master = to_dw_i3c_master(m);
1071 master->regs +
1072 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
1075 master->addrs[data->index] = 0;
1076 master->free_pos |= BIT(data->index);
1082 struct dw_i3c_master *master = dev_id;
1085 status = readl(master->regs + INTR_STATUS);
1087 if (!(status & readl(master->regs + INTR_STATUS_EN))) {
1088 writel(INTR_ALL, master->regs + INTR_STATUS);
1092 spin_lock(&master->xferqueue.lock);
1093 dw_i3c_master_end_xfer_locked(master, status);
1095 writel(INTR_TRANSFER_ERR_STAT, master->regs + INTR_STATUS);
1096 spin_unlock(&master->xferqueue.lock);
1118 struct dw_i3c_master *master;
1121 master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL);
1122 if (!master)
1125 master->regs = devm_platform_ioremap_resource(pdev, 0);
1126 if (IS_ERR(master->regs))
1127 return PTR_ERR(master->regs);
1129 master->core_clk = devm_clk_get(&pdev->dev, NULL);
1130 if (IS_ERR(master->core_clk))
1131 return PTR_ERR(master->core_clk);
1133 master->core_rst = devm_reset_control_get_optional_exclusive(&pdev->dev,
1135 if (IS_ERR(master->core_rst))
1136 return PTR_ERR(master->core_rst);
1138 ret = clk_prepare_enable(master->core_clk);
1142 reset_control_deassert(master->core_rst);
1144 spin_lock_init(&master->xferqueue.lock);
1145 INIT_LIST_HEAD(&master->xferqueue.list);
1147 writel(INTR_ALL, master->regs + INTR_STATUS);
1151 dev_name(&pdev->dev), master);
1155 platform_set_drvdata(pdev, master);
1158 ret = readl(master->regs + QUEUE_STATUS_LEVEL);
1159 master->caps.cmdfifodepth = QUEUE_STATUS_LEVEL_CMD(ret);
1161 ret = readl(master->regs + DATA_BUFFER_STATUS_LEVEL);
1162 master->caps.datafifodepth = DATA_BUFFER_STATUS_LEVEL_TX(ret);
1164 ret = readl(master->regs + DEVICE_ADDR_TABLE_POINTER);
1165 master->datstartaddr = ret;
1166 master->maxdevs = ret >> 16;
1167 master->free_pos = GENMASK(master->maxdevs - 1, 0);
1169 ret = i3c_master_register(&master->base, &pdev->dev,
1177 reset_control_assert(master->core_rst);
1180 clk_disable_unprepare(master->core_clk);
1187 struct dw_i3c_master *master = platform_get_drvdata(pdev);
1190 ret = i3c_master_unregister(&master->base);
1194 reset_control_assert(master->core_rst);
1196 clk_disable_unprepare(master->core_clk);
1202 { .compatible = "snps,dw-i3c-master-1.00a", },
1211 .name = "dw-i3c-master",