Lines Matching defs:i2c_dev
93 static int wmt_i2c_wait_bus_not_busy(struct wmt_i2c_dev *i2c_dev)
98 while (!(readw(i2c_dev->base + REG_CSR) & CSR_READY_MASK)) {
100 dev_warn(i2c_dev->dev, "timeout waiting for bus ready\n");
109 static int wmt_check_status(struct wmt_i2c_dev *i2c_dev)
113 if (i2c_dev->cmd_status & ISR_NACK_ADDR)
116 if (i2c_dev->cmd_status & ISR_SCL_TIMEOUT)
125 struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
132 ret = wmt_i2c_wait_bus_not_busy(i2c_dev);
143 writew(0, i2c_dev->base + REG_CDR);
145 writew(pmsg->buf[0] & 0xFF, i2c_dev->base + REG_CDR);
149 val = readw(i2c_dev->base + REG_CR);
151 writew(val, i2c_dev->base + REG_CR);
153 val = readw(i2c_dev->base + REG_CR);
155 writew(val, i2c_dev->base + REG_CR);
158 reinit_completion(&i2c_dev->complete);
160 if (i2c_dev->mode == I2C_MODE_STANDARD)
167 writew(tcr_val, i2c_dev->base + REG_TCR);
170 val = readw(i2c_dev->base + REG_CR);
172 writew(val, i2c_dev->base + REG_CR);
176 wait_result = wait_for_completion_timeout(&i2c_dev->complete,
182 ret = wmt_check_status(i2c_dev);
188 val = readw(i2c_dev->base + REG_CSR);
190 dev_dbg(i2c_dev->dev, "write RCV NACK error\n");
196 writew(val, i2c_dev->base + REG_CR);
202 writew(CR_ENABLE, i2c_dev->base + REG_CR);
204 writew(pmsg->buf[xfer_len] & 0xFF, i2c_dev->base +
206 writew(CR_CPU_RDY | CR_ENABLE, i2c_dev->base + REG_CR);
216 struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
223 ret = wmt_i2c_wait_bus_not_busy(i2c_dev);
228 val = readw(i2c_dev->base + REG_CR);
230 writew(val, i2c_dev->base + REG_CR);
232 val = readw(i2c_dev->base + REG_CR);
234 writew(val, i2c_dev->base + REG_CR);
237 val = readw(i2c_dev->base + REG_CR);
239 writew(val, i2c_dev->base + REG_CR);
243 val = readw(i2c_dev->base + REG_CR);
245 writew(val, i2c_dev->base + REG_CR);
248 reinit_completion(&i2c_dev->complete);
250 if (i2c_dev->mode == I2C_MODE_STANDARD)
257 writew(tcr_val, i2c_dev->base + REG_TCR);
260 val = readw(i2c_dev->base + REG_CR);
262 writew(val, i2c_dev->base + REG_CR);
266 wait_result = wait_for_completion_timeout(&i2c_dev->complete,
272 ret = wmt_check_status(i2c_dev);
276 pmsg->buf[xfer_len] = readw(i2c_dev->base + REG_CDR) >> 8;
280 val = readw(i2c_dev->base + REG_CR);
282 writew(val, i2c_dev->base + REG_CR);
284 val = readw(i2c_dev->base + REG_CR);
286 writew(val, i2c_dev->base + REG_CR);
326 struct wmt_i2c_dev *i2c_dev = data;
329 i2c_dev->cmd_status = readw(i2c_dev->base + REG_ISR);
330 writew(i2c_dev->cmd_status, i2c_dev->base + REG_ISR);
332 complete(&i2c_dev->complete);
337 static int wmt_i2c_reset_hardware(struct wmt_i2c_dev *i2c_dev)
341 err = clk_prepare_enable(i2c_dev->clk);
343 dev_err(i2c_dev->dev, "failed to enable clock\n");
347 err = clk_set_rate(i2c_dev->clk, 20000000);
349 dev_err(i2c_dev->dev, "failed to set clock = 20Mhz\n");
350 clk_disable_unprepare(i2c_dev->clk);
354 writew(0, i2c_dev->base + REG_CR);
355 writew(MCR_APB_166M, i2c_dev->base + REG_MCR);
356 writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR);
357 writew(IMR_ENABLE_ALL, i2c_dev->base + REG_IMR);
358 writew(CR_ENABLE, i2c_dev->base + REG_CR);
359 readw(i2c_dev->base + REG_CSR); /* read clear */
360 writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR);
362 if (i2c_dev->mode == I2C_MODE_STANDARD)
363 writew(SCL_TIMEOUT(128) | TR_STD, i2c_dev->base + REG_TR);
365 writew(SCL_TIMEOUT(128) | TR_HS, i2c_dev->base + REG_TR);
373 struct wmt_i2c_dev *i2c_dev;
379 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
380 if (!i2c_dev)
384 i2c_dev->base = devm_ioremap_resource(&pdev->dev, res);
385 if (IS_ERR(i2c_dev->base))
386 return PTR_ERR(i2c_dev->base);
388 i2c_dev->irq = irq_of_parse_and_map(np, 0);
389 if (!i2c_dev->irq) {
394 i2c_dev->clk = of_clk_get(np, 0);
395 if (IS_ERR(i2c_dev->clk)) {
397 return PTR_ERR(i2c_dev->clk);
400 i2c_dev->mode = I2C_MODE_STANDARD;
403 i2c_dev->mode = I2C_MODE_FAST;
405 i2c_dev->dev = &pdev->dev;
407 err = devm_request_irq(&pdev->dev, i2c_dev->irq, wmt_i2c_isr, 0,
408 "i2c", i2c_dev);
410 dev_err(&pdev->dev, "failed to request irq %i\n", i2c_dev->irq);
414 adap = &i2c_dev->adapter;
415 i2c_set_adapdata(adap, i2c_dev);
422 init_completion(&i2c_dev->complete);
424 err = wmt_i2c_reset_hardware(i2c_dev);
434 platform_set_drvdata(pdev, i2c_dev);
441 struct wmt_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
444 writew(0, i2c_dev->base + REG_IMR);
445 clk_disable_unprepare(i2c_dev->clk);
446 i2c_del_adapter(&i2c_dev->adapter);