Lines Matching defs:i2c_dev
298 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
301 writel_relaxed(val, i2c_dev->base + reg);
304 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned int reg)
306 return readl_relaxed(i2c_dev->base + reg);
313 static u32 tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev, unsigned int reg)
315 if (i2c_dev->is_dvc)
317 else if (i2c_dev->is_vi)
323 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned int reg)
325 writel_relaxed(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
329 readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
330 else if (i2c_dev->is_vi)
331 readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, I2C_INT_STATUS));
334 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned int reg)
336 return readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
339 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
342 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
345 static void i2c_writesl_vi(struct tegra_i2c_dev *i2c_dev, void *data,
357 i2c_writel(i2c_dev, *data32++, reg);
360 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
363 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
366 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
370 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) & ~mask;
371 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
374 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
378 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) | mask;
379 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
384 struct tegra_i2c_dev *i2c_dev = args;
386 complete(&i2c_dev->dma_complete);
389 static int tegra_i2c_dma_submit(struct tegra_i2c_dev *i2c_dev, size_t len)
395 dev_dbg(i2c_dev->dev, "starting DMA for length: %zu\n", len);
397 reinit_completion(&i2c_dev->dma_complete);
399 dir = i2c_dev->msg_read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
400 chan = i2c_dev->msg_read ? i2c_dev->rx_dma_chan : i2c_dev->tx_dma_chan;
402 dma_desc = dmaengine_prep_slave_single(chan, i2c_dev->dma_phys,
406 dev_err(i2c_dev->dev, "failed to get %s DMA descriptor\n",
407 i2c_dev->msg_read ? "RX" : "TX");
412 dma_desc->callback_param = i2c_dev;
420 static void tegra_i2c_release_dma(struct tegra_i2c_dev *i2c_dev)
422 if (i2c_dev->dma_buf) {
423 dma_free_coherent(i2c_dev->dma_dev, i2c_dev->dma_buf_size,
424 i2c_dev->dma_buf, i2c_dev->dma_phys);
425 i2c_dev->dma_buf = NULL;
428 if (i2c_dev->tx_dma_chan) {
429 dma_release_channel(i2c_dev->tx_dma_chan);
430 i2c_dev->tx_dma_chan = NULL;
433 if (i2c_dev->rx_dma_chan) {
434 dma_release_channel(i2c_dev->rx_dma_chan);
435 i2c_dev->rx_dma_chan = NULL;
439 static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev)
446 if (!i2c_dev->hw->has_apb_dma || i2c_dev->is_vi)
450 dev_dbg(i2c_dev->dev, "DMA support not enabled\n");
454 chan = dma_request_chan(i2c_dev->dev, "rx");
460 i2c_dev->rx_dma_chan = chan;
462 chan = dma_request_chan(i2c_dev->dev, "tx");
468 i2c_dev->tx_dma_chan = chan;
470 WARN_ON(i2c_dev->tx_dma_chan->device != i2c_dev->rx_dma_chan->device);
471 i2c_dev->dma_dev = chan->device->dev;
473 i2c_dev->dma_buf_size = i2c_dev->hw->quirks->max_write_len +
476 dma_buf = dma_alloc_coherent(i2c_dev->dma_dev, i2c_dev->dma_buf_size,
479 dev_err(i2c_dev->dev, "failed to allocate DMA buffer\n");
484 i2c_dev->dma_buf = dma_buf;
485 i2c_dev->dma_phys = dma_phys;
490 tegra_i2c_release_dma(i2c_dev);
492 dev_err(i2c_dev->dev, "cannot use DMA: %d\n", err);
493 dev_err(i2c_dev->dev, "falling back to PIO\n");
507 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
511 val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
514 dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
516 val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
518 dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
521 static void tegra_i2c_vi_init(struct tegra_i2c_dev *i2c_dev)
527 i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_0);
533 i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_1);
537 i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_0);
542 i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_1);
545 i2c_writel(i2c_dev, value, I2C_BUS_CLEAR_CNFG);
547 i2c_writel(i2c_dev, 0x0, I2C_TLOW_SEXT);
550 static int tegra_i2c_poll_register(struct tegra_i2c_dev *i2c_dev,
554 void __iomem *addr = i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg);
557 if (!i2c_dev->atomic_mode && !in_irq())
565 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
570 if (i2c_dev->hw->has_mst_fifo) {
580 val = i2c_readl(i2c_dev, offset);
582 i2c_writel(i2c_dev, val, offset);
584 err = tegra_i2c_poll_register(i2c_dev, offset, mask, 1000, 1000000);
586 dev_err(i2c_dev->dev, "failed to flush FIFO\n");
593 static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev)
597 if (!i2c_dev->hw->has_config_load_reg)
600 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD);
602 err = tegra_i2c_poll_register(i2c_dev, I2C_CONFIG_LOAD, 0xffffffff,
605 dev_err(i2c_dev->dev, "failed to load config\n");
612 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
625 err = reset_control_reset(i2c_dev->rst);
628 if (i2c_dev->is_dvc)
629 tegra_dvc_init(i2c_dev);
634 if (i2c_dev->hw->has_multi_master_mode)
637 i2c_writel(i2c_dev, val, I2C_CNFG);
638 i2c_writel(i2c_dev, 0, I2C_INT_MASK);
640 if (i2c_dev->is_vi)
641 tegra_i2c_vi_init(i2c_dev);
643 switch (i2c_dev->bus_clk_rate) {
646 tlow = i2c_dev->hw->tlow_fast_fastplus_mode;
647 thigh = i2c_dev->hw->thigh_fast_fastplus_mode;
648 tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode;
650 if (i2c_dev->bus_clk_rate > I2C_MAX_FAST_MODE_FREQ)
651 non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode;
653 non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode;
657 tlow = i2c_dev->hw->tlow_std_mode;
658 thigh = i2c_dev->hw->thigh_std_mode;
659 tsu_thd = i2c_dev->hw->setup_hold_time_std_mode;
660 non_hs_mode = i2c_dev->hw->clk_divisor_std_mode;
666 i2c_dev->hw->clk_divisor_hs_mode) |
668 i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
670 if (i2c_dev->hw->has_interface_timing_reg) {
673 i2c_writel(i2c_dev, val, I2C_INTERFACE_TIMING_0);
680 if (i2c_dev->hw->has_interface_timing_reg && tsu_thd)
681 i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1);
685 err = clk_set_rate(i2c_dev->div_clk,
686 i2c_dev->bus_clk_rate * clk_multiplier);
688 dev_err(i2c_dev->dev, "failed to set div-clk rate: %d\n", err);
692 if (!i2c_dev->is_dvc && !i2c_dev->is_vi) {
693 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
696 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
697 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
698 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
701 err = tegra_i2c_flush_fifos(i2c_dev);
705 if (i2c_dev->multimaster_mode && i2c_dev->hw->has_slcg_override_reg)
706 i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE);
708 err = tegra_i2c_wait_for_config_load(i2c_dev);
715 static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev)
725 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
727 cnfg = i2c_readl(i2c_dev, I2C_CNFG);
729 i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, I2C_CNFG);
731 return tegra_i2c_wait_for_config_load(i2c_dev);
734 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
736 size_t buf_remaining = i2c_dev->msg_buf_remaining;
738 u8 *buf = i2c_dev->msg_buf;
745 if (WARN_ON_ONCE(!(i2c_dev->msg_buf_remaining)))
748 if (i2c_dev->hw->has_mst_fifo) {
749 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS);
752 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
761 i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
777 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
788 i2c_dev->msg_buf_remaining = buf_remaining;
789 i2c_dev->msg_buf = buf;
794 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
796 size_t buf_remaining = i2c_dev->msg_buf_remaining;
798 u8 *buf = i2c_dev->msg_buf;
801 if (i2c_dev->hw->has_mst_fifo) {
802 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS);
805 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
832 i2c_dev->msg_buf_remaining = buf_remaining;
833 i2c_dev->msg_buf = buf + words_to_transfer * BYTES_PER_FIFO_WORD;
835 if (i2c_dev->is_vi)
836 i2c_writesl_vi(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
838 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
857 i2c_dev->msg_buf_remaining = 0;
858 i2c_dev->msg_buf = NULL;
860 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
869 struct tegra_i2c_dev *i2c_dev = dev_id;
872 status = i2c_readl(i2c_dev, I2C_INT_STATUS);
875 dev_warn(i2c_dev->dev, "IRQ status 0 %08x %08x %08x\n",
876 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
877 i2c_readl(i2c_dev, I2C_STATUS),
878 i2c_readl(i2c_dev, I2C_CNFG));
879 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
884 tegra_i2c_disable_packet_mode(i2c_dev);
886 i2c_dev->msg_err |= I2C_ERR_NO_ACK;
888 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
896 if (i2c_dev->hw->supports_bus_clear && (status & I2C_INT_BUS_CLR_DONE))
899 if (!i2c_dev->dma_mode) {
900 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
901 if (tegra_i2c_empty_rx_fifo(i2c_dev)) {
907 i2c_dev->msg_err |= I2C_ERR_RX_BUFFER_OVERFLOW;
912 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
913 if (i2c_dev->msg_buf_remaining)
914 tegra_i2c_fill_tx_fifo(i2c_dev);
916 tegra_i2c_mask_irq(i2c_dev,
921 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
922 if (i2c_dev->is_dvc)
923 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
934 if (i2c_dev->dma_mode)
935 i2c_dev->msg_buf_remaining = 0;
940 if (WARN_ON_ONCE(i2c_dev->msg_buf_remaining)) {
941 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
944 complete(&i2c_dev->msg_complete);
949 tegra_i2c_mask_irq(i2c_dev,
956 if (i2c_dev->hw->supports_bus_clear)
957 tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
959 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
961 if (i2c_dev->is_dvc)
962 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
964 if (i2c_dev->dma_mode) {
965 if (i2c_dev->msg_read)
966 dmaengine_terminate_async(i2c_dev->rx_dma_chan);
968 dmaengine_terminate_async(i2c_dev->tx_dma_chan);
970 complete(&i2c_dev->dma_complete);
973 complete(&i2c_dev->msg_complete);
978 static void tegra_i2c_config_fifo_trig(struct tegra_i2c_dev *i2c_dev,
986 if (i2c_dev->hw->has_mst_fifo)
991 if (i2c_dev->dma_mode) {
999 if (i2c_dev->msg_read) {
1000 chan = i2c_dev->rx_dma_chan;
1001 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_RX_FIFO);
1003 slv_config.src_addr = i2c_dev->base_phys + reg_offset;
1007 if (i2c_dev->hw->has_mst_fifo)
1012 chan = i2c_dev->tx_dma_chan;
1013 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_TX_FIFO);
1015 slv_config.dst_addr = i2c_dev->base_phys + reg_offset;
1019 if (i2c_dev->hw->has_mst_fifo)
1028 dev_err(i2c_dev->dev, "DMA config failed: %d\n", err);
1029 dev_err(i2c_dev->dev, "falling back to PIO\n");
1031 tegra_i2c_release_dma(i2c_dev);
1032 i2c_dev->dma_mode = false;
1038 if (i2c_dev->hw->has_mst_fifo)
1045 i2c_writel(i2c_dev, val, reg);
1048 static unsigned long tegra_i2c_poll_completion(struct tegra_i2c_dev *i2c_dev,
1056 u32 status = i2c_readl(i2c_dev, I2C_INT_STATUS);
1059 tegra_i2c_isr(i2c_dev->irq, i2c_dev);
1074 static unsigned long tegra_i2c_wait_completion(struct tegra_i2c_dev *i2c_dev,
1080 if (i2c_dev->atomic_mode) {
1081 ret = tegra_i2c_poll_completion(i2c_dev, complete, timeout_ms);
1083 enable_irq(i2c_dev->irq);
1086 disable_irq(i2c_dev->irq);
1099 ret = tegra_i2c_poll_completion(i2c_dev, complete, 0);
1107 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1111 reinit_completion(&i2c_dev->msg_complete);
1115 i2c_writel(i2c_dev, val, I2C_BUS_CLEAR_CNFG);
1117 err = tegra_i2c_wait_for_config_load(i2c_dev);
1122 i2c_writel(i2c_dev, val, I2C_BUS_CLEAR_CNFG);
1123 tegra_i2c_unmask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
1125 time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete, 50);
1126 tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
1129 dev_err(i2c_dev->dev, "failed to clear bus\n");
1133 val = i2c_readl(i2c_dev, I2C_BUS_CLEAR_STATUS);
1135 dev_err(i2c_dev->dev, "un-recovered arbitration lost\n");
1142 static void tegra_i2c_push_packet_header(struct tegra_i2c_dev *i2c_dev,
1146 u32 *dma_buf = i2c_dev->dma_buf;
1152 FIELD_PREP(PACKET_HEADER0_CONT_ID, i2c_dev->cont_id) |
1155 if (i2c_dev->dma_mode && !i2c_dev->msg_read)
1158 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1162 if (i2c_dev->dma_mode && !i2c_dev->msg_read)
1165 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1187 if (i2c_dev->dma_mode && !i2c_dev->msg_read)
1190 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1193 static int tegra_i2c_error_recover(struct tegra_i2c_dev *i2c_dev,
1196 if (i2c_dev->msg_err == I2C_ERR_NONE)
1199 tegra_i2c_init(i2c_dev);
1202 if (i2c_dev->msg_err == I2C_ERR_ARBITRATION_LOST) {
1203 if (!i2c_dev->multimaster_mode)
1204 return i2c_recover_bus(&i2c_dev->adapter);
1209 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
1219 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
1228 err = tegra_i2c_flush_fifos(i2c_dev);
1232 i2c_dev->msg_buf = msg->buf;
1233 i2c_dev->msg_buf_remaining = msg->len;
1234 i2c_dev->msg_err = I2C_ERR_NONE;
1235 i2c_dev->msg_read = !!(msg->flags & I2C_M_RD);
1236 reinit_completion(&i2c_dev->msg_complete);
1238 if (i2c_dev->msg_read)
1245 i2c_dev->dma_mode = xfer_size > I2C_PIO_MODE_PREFERRED_LEN &&
1246 i2c_dev->dma_buf && !i2c_dev->atomic_mode;
1248 tegra_i2c_config_fifo_trig(i2c_dev, xfer_size);
1255 i2c_dev->bus_clk_rate);
1258 tegra_i2c_unmask_irq(i2c_dev, int_mask);
1260 if (i2c_dev->dma_mode) {
1261 if (i2c_dev->msg_read) {
1262 dma_sync_single_for_device(i2c_dev->dma_dev,
1263 i2c_dev->dma_phys,
1266 err = tegra_i2c_dma_submit(i2c_dev, xfer_size);
1270 dma_sync_single_for_cpu(i2c_dev->dma_dev,
1271 i2c_dev->dma_phys,
1276 tegra_i2c_push_packet_header(i2c_dev, msg, end_state);
1278 if (!i2c_dev->msg_read) {
1279 if (i2c_dev->dma_mode) {
1280 memcpy(i2c_dev->dma_buf + I2C_PACKET_HEADER_SIZE,
1283 dma_sync_single_for_device(i2c_dev->dma_dev,
1284 i2c_dev->dma_phys,
1287 err = tegra_i2c_dma_submit(i2c_dev, xfer_size);
1291 tegra_i2c_fill_tx_fifo(i2c_dev);
1295 if (i2c_dev->hw->has_per_pkt_xfer_complete_irq)
1298 if (!i2c_dev->dma_mode) {
1301 else if (i2c_dev->msg_buf_remaining)
1305 tegra_i2c_unmask_irq(i2c_dev, int_mask);
1306 dev_dbg(i2c_dev->dev, "unmasked IRQ: %02x\n",
1307 i2c_readl(i2c_dev, I2C_INT_MASK));
1309 if (i2c_dev->dma_mode) {
1310 time_left = tegra_i2c_wait_completion(i2c_dev,
1311 &i2c_dev->dma_complete,
1319 dmaengine_synchronize(i2c_dev->msg_read ?
1320 i2c_dev->rx_dma_chan :
1321 i2c_dev->tx_dma_chan);
1323 dmaengine_terminate_sync(i2c_dev->msg_read ?
1324 i2c_dev->rx_dma_chan :
1325 i2c_dev->tx_dma_chan);
1327 if (!time_left && !completion_done(&i2c_dev->dma_complete)) {
1328 dev_err(i2c_dev->dev, "DMA transfer timed out\n");
1329 tegra_i2c_init(i2c_dev);
1333 if (i2c_dev->msg_read && i2c_dev->msg_err == I2C_ERR_NONE) {
1334 dma_sync_single_for_cpu(i2c_dev->dma_dev,
1335 i2c_dev->dma_phys,
1338 memcpy(i2c_dev->msg_buf, i2c_dev->dma_buf, msg->len);
1342 time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete,
1345 tegra_i2c_mask_irq(i2c_dev, int_mask);
1348 dev_err(i2c_dev->dev, "I2C transfer timed out\n");
1349 tegra_i2c_init(i2c_dev);
1353 dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n",
1354 time_left, completion_done(&i2c_dev->msg_complete),
1355 i2c_dev->msg_err);
1357 i2c_dev->dma_mode = false;
1359 err = tegra_i2c_error_recover(i2c_dev, msg);
1369 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1372 ret = pm_runtime_get_sync(i2c_dev->dev);
1374 dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret);
1375 pm_runtime_put_noidle(i2c_dev->dev);
1389 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type);
1394 pm_runtime_put(i2c_dev->dev);
1402 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1405 i2c_dev->atomic_mode = true;
1407 i2c_dev->atomic_mode = false;
1414 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1418 if (i2c_dev->hw->has_continue_xfer_support)
1628 static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev)
1630 struct device_node *np = i2c_dev->dev->of_node;
1635 &i2c_dev->bus_clk_rate);
1637 i2c_dev->bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ;
1640 i2c_dev->multimaster_mode = multi_mode;
1643 i2c_dev->is_dvc = true;
1646 i2c_dev->is_vi = true;
1649 static int tegra_i2c_init_clocks(struct tegra_i2c_dev *i2c_dev)
1653 i2c_dev->clocks[i2c_dev->nclocks++].id = "div-clk";
1655 if (i2c_dev->hw == &tegra20_i2c_hw || i2c_dev->hw == &tegra30_i2c_hw)
1656 i2c_dev->clocks[i2c_dev->nclocks++].id = "fast-clk";
1658 if (i2c_dev->is_vi)
1659 i2c_dev->clocks[i2c_dev->nclocks++].id = "slow";
1661 err = devm_clk_bulk_get(i2c_dev->dev, i2c_dev->nclocks,
1662 i2c_dev->clocks);
1666 err = clk_bulk_prepare(i2c_dev->nclocks, i2c_dev->clocks);
1670 i2c_dev->div_clk = i2c_dev->clocks[0].clk;
1672 if (!i2c_dev->multimaster_mode)
1675 err = clk_enable(i2c_dev->div_clk);
1677 dev_err(i2c_dev->dev, "failed to enable div-clk: %d\n", err);
1684 clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks);
1689 static void tegra_i2c_release_clocks(struct tegra_i2c_dev *i2c_dev)
1691 if (i2c_dev->multimaster_mode)
1692 clk_disable(i2c_dev->div_clk);
1694 clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks);
1697 static int tegra_i2c_init_hardware(struct tegra_i2c_dev *i2c_dev)
1701 ret = pm_runtime_get_sync(i2c_dev->dev);
1703 dev_err(i2c_dev->dev, "runtime resume failed: %d\n", ret);
1705 ret = tegra_i2c_init(i2c_dev);
1707 pm_runtime_put(i2c_dev->dev);
1714 struct tegra_i2c_dev *i2c_dev;
1718 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
1719 if (!i2c_dev)
1722 platform_set_drvdata(pdev, i2c_dev);
1724 init_completion(&i2c_dev->msg_complete);
1725 init_completion(&i2c_dev->dma_complete);
1727 i2c_dev->hw = of_device_get_match_data(&pdev->dev);
1728 i2c_dev->cont_id = pdev->id;
1729 i2c_dev->dev = &pdev->dev;
1731 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1732 if (IS_ERR(i2c_dev->base))
1733 return PTR_ERR(i2c_dev->base);
1735 i2c_dev->base_phys = res->start;
1741 i2c_dev->irq = err;
1744 irq_set_status_flags(i2c_dev->irq, IRQ_NOAUTOEN);
1746 err = devm_request_irq(i2c_dev->dev, i2c_dev->irq, tegra_i2c_isr,
1747 IRQF_NO_SUSPEND, dev_name(i2c_dev->dev),
1748 i2c_dev);
1752 i2c_dev->rst = devm_reset_control_get_exclusive(i2c_dev->dev, "i2c");
1753 if (IS_ERR(i2c_dev->rst)) {
1754 dev_err_probe(i2c_dev->dev, PTR_ERR(i2c_dev->rst),
1756 return PTR_ERR(i2c_dev->rst);
1759 tegra_i2c_parse_dt(i2c_dev);
1761 err = tegra_i2c_init_clocks(i2c_dev);
1765 err = tegra_i2c_init_dma(i2c_dev);
1778 if (!i2c_dev->is_vi)
1779 pm_runtime_irq_safe(i2c_dev->dev);
1781 pm_runtime_enable(i2c_dev->dev);
1783 err = tegra_i2c_init_hardware(i2c_dev);
1787 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
1788 i2c_dev->adapter.dev.of_node = i2c_dev->dev->of_node;
1789 i2c_dev->adapter.dev.parent = i2c_dev->dev;
1790 i2c_dev->adapter.retries = 1;
1791 i2c_dev->adapter.timeout = 6 * HZ;
1792 i2c_dev->adapter.quirks = i2c_dev->hw->quirks;
1793 i2c_dev->adapter.owner = THIS_MODULE;
1794 i2c_dev->adapter.class = I2C_CLASS_DEPRECATED;
1795 i2c_dev->adapter.algo = &tegra_i2c_algo;
1796 i2c_dev->adapter.nr = pdev->id;
1798 if (i2c_dev->hw->supports_bus_clear)
1799 i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info;
1801 strlcpy(i2c_dev->adapter.name, dev_name(i2c_dev->dev),
1802 sizeof(i2c_dev->adapter.name));
1804 err = i2c_add_numbered_adapter(&i2c_dev->adapter);
1811 pm_runtime_disable(i2c_dev->dev);
1813 tegra_i2c_release_dma(i2c_dev);
1815 tegra_i2c_release_clocks(i2c_dev);
1822 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
1824 i2c_del_adapter(&i2c_dev->adapter);
1825 pm_runtime_disable(i2c_dev->dev);
1827 tegra_i2c_release_dma(i2c_dev);
1828 tegra_i2c_release_clocks(i2c_dev);
1835 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1842 err = clk_bulk_enable(i2c_dev->nclocks, i2c_dev->clocks);
1851 if (i2c_dev->is_vi) {
1852 err = tegra_i2c_init(i2c_dev);
1860 clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks);
1867 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1869 clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks);
1876 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1879 i2c_mark_adapter_suspended(&i2c_dev->adapter);
1892 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1903 err = tegra_i2c_init(i2c_dev);
1918 i2c_mark_adapter_resumed(&i2c_dev->adapter);